DRA821U-Q1: Fail to bootup

Does not boot anymore - are all the processor power rails energized, and reset is de-asserted?

I don't have full knowledge of your processor and PMIC connections.  SYS_MCU_PWRDN - is this controlled from processor IO?  SYS_MCU_EN - does this control the PMIC enable?  Are you using TPS65941111 for PMIC?

Assuming those are yes - SYS_MCU_PWRDN goes low (software command) - causing SYS_MCU_EN to drive low disabling PMIC.  PMIC begins shutdown sequence - which includes asserting processor reset.  The processor reset causes the IO to be tri-stated, thus SYS_MCU_PWRDN is tri-stated and the pull-up R302 pulls signal high, which again enables SYS_MCU_EN.

It is possible the PMIC is re-enabled (ENABLE driven high) before the shutdown sequence is completed.  Can you confirm?  I'll loop PMIC resource to see if this is an issue.

It is possible the PMIC attempts to restart - but detects residual voltage on some of the power rails (as they have not had time to fully discharge), detects and error and enters a safe state (which processor is turned off).  Can you confirm?

Hi Robert,

Does not boot anymore - are all the processor power rails energized, and reset is de-asserted? yes, all power rails ok, and reset is high.

our A sample design, SYS_MCU_PWRDN is not used. yes.,  SYS_MCU_EN is enabling PMIC A

we use TPS6594141BRWERQ1 and LP876441B1RQKRQ1

BTW, this case happened very rare, cannot be constantly reproduceable.

I can share out schematic design if you provide shared box link.

Thanks

Max

Can you check RESETSTATz (reset output)?  This will confirm the device exits the internal reset seqeunce.

What is your boot source?  Is booting started and failing, or never started/  For failing condition, have you connected with JTAG to see status of processor?  That is probably next recommended step.

I will try to reproduce the scenario, it is hard though.

we boot from eMMC, backup is USB DFU, we have not use JTGA yet

Thanks

Max