AM62P-Q1: LPDDR4 configuration settings

Vishwajit,

1a. MR2[7] is only set during write leveling, which is a very short period of time during initialization.  Write leveling is performed during the DDR initialization procedure.

1b. The last i heard it will be available in SDK11.2, but this is subject to change.  Right now, you would need to set the max operating temperature in the DDR register configuration tool to operate at higher temperatures, until that feature is available

2.  You need to put the device in a low power mode to initiate self refresh.  Instructions were sent to Susan by Suren via email

3. Per Bank refreshes are not enabled and not supported, only all bank refreshes are performed.  For self-refresh command to be observed, you need to put the device in a low power mode as stated earlier.

Regards,

James

HI James,

1.a. OK, Understood. Thanks.

If I am not wrong, I think as per Micron SITA measurement observation they did not see this bit is set during the DDR Initialization procedure,

So, in that case can you let us know, how we can set this bit?

2. we are not sure what you mean by “put the device in low power mode”. Can you please elaborate? & why it required what its purpose etc.

3. Ok, Understood, thank you, can you answer to question #2 above about low power mode?

Regards

Bharath

1.  Have them perform a logic analyzer trace of the MR commands during initialization, they should see that bit set.  The bit is not user controllable, it is set/cleared during the initialization phase which is all hardware controlled.  

2. Please refer to the email sent to Susan by Suren.  The processor needs to be in a low power mode to initiate a self-refresh command

Regards,

James

Thanks James for the reply. Following are my comments:

1. The Micron report didn't show MR2 bit 7 being set and I do agree with you that probably Micron didn't check it during initialization. 

Write leveling can be done on each power-up, or it may be done as a one-time event and then saved to internal memory.  It seems that you are implying that TI does it during initialization. According to Micron's report, the Data Mask is well centered top-to-bottom, so the selected VrefDQ value is valid. We should be OK with the current implementation.

2. Putting LP4 in low power mode is NOT a common implementation in Automotive where aggressive power savings are not always needed.  Mobile uses every power savings feature possible for obvious reasons.

CKE won't go low if we don't enter low power mode which is NOT required, same applies to self refresh. 

3. I have enabled "Periodic ZQ" calibration to compensate for signal drift over PVT but I wanted to check if this is really needed based on your internal validation.

Did your internal validation show that the need for periodic ZQ calibration or is it only needed during initialization? Please advise.

4. Looking forward for the SDK release that implements the MR4 command. This would prevent additional power draw and bandwidth reduction.

Regards,

Susan

Hi Susan

1. Yes Write Leveling is performed on every DDR initialization

2. So then i don't think you would need to check any self-refresh related timing parameters

3. This is a question for the memory vendor.  We have typically seen memory vendors recommending this being enabled for automotive applications across -40-125C temperatures.  Our validation was performed with this disabled

Regards,

James