AM4378: problem in loading PRU-ICSS firmware in the AM4378 processor

thanks for your reply.
This issue resolved but I can't use my driver because I haven't any resource manual for developing a standard firmware. 
Examples contain a loopback test but I don't know a standard structure for a firmware and which functions should be developed in it.

Hello Moh,

Please explain more about exactly what you are trying to do in your system.

For example, do you just need an additional UART port from Linux, and you want Linux to be able to use the hardware UART in the PRU subsystem? If that is the case, then you do not actually need to program the PRU core. You can just program Linux. You'll see the Linux driver for AM335x, and you could modify the driver and devicetree file to add support for the same software in AM437x: https://software-dl.ti.com/processor-sdk-linux/esd/AM335X/09_03_05_02/exports/docs/linux/Foundational_Components/PRU-ICSS/Linux_Drivers/pruss-uart.html

If you are doing something else, please explain the usecase.

Regards,

Nick

I need an additional UART port from Linux that controlled by PRU core not main core. I previously launch hardware UART in the PRU subsystem using 8250_pruss.c driver, but the performance of this additional uart is not sufficient for my application because of hardware limitations. I want an additional uart port that works same as main uart ports or better in terms of real time response.

Hello Moh,

Please correct me if I am misunderstanding anything:

1) You want something to be able to listen to inputs on a UART port, and then respond quickly (i.e., have a good "real time response")

2) When Linux is controlling a UART port, Linux does not respond fast enough, even when running RT Linux

Followup questions:

1) What is the "cycle time" that you need? (how much time between when the UART signal arrives at the processor, and when an action needs to occur?)

2) What is the action that needs to occur after the UART input?

3) Is there inter-processor communication (IPC) that needs to happen between Linux and the PRU cores? If so, does this IPC need to occur during the cycle time?

Regards,

Nick

The main UARTs function correctly, but an additional PRU UART, controlled by the main processor, fails to respond properly under high bus load. This issue arises because its FIFO size is only 16 bytes, compared to the 64-byte FIFO size of the main UARTs, and the main processor is unable to handle its interrupts effectively. I suspect that if the additional PRU UART were controlled by the PRU core, the problem could be resolved.

During my test, the frequency of received packets was 200 Hz. No significant processing was performed within this cycle, apart from calculating the CRC check for approximately 120 bytes of received packets. However, around 1% of packets were not received correctly due to the loss of some bytes.

I don't have any inter-processor communication in my project.