TDA4VEN-Q1: ECC of DDR system

Hi,

Please elaborate a bit more on what is the goal here? DDR has inline ECC. Once you enable 1/8th of the memory(DDR) will be reserved for Inline ECC.

- Keerthy

Hi Keerthy-san

Thank you for your answer.

And I do not fully understand the DDR system(especially inline ECC) and apologize for asking such a basic question.

The questions I wanted to ask were: Do I need to provide separate DRAM device for ECC? And how much capacity is needed for ECC?

I understand that only one DRAM component is required and memory capacity is 4Gb for inline ECC(In case of using 32Gb memory) from your answer.

Is it correct above my understanding?

Hi Furuna,

Yes, the DDRSS SDRAM ECC is inline with the data, meaning that the ECC codes and the data share the same physical DQ IO , and are interfaced to the same physical LPDDR4 memory on the PCB.

Because the same physical LPDDR4 memory is shared between the ECC codes and data, ~ 1/8th of physical LPDDR4 memory space will be reserved for the ECC codes, implying that your system will only have access to ~ 7/8ths of the LPDDR4 space.

Regards,
Kevin