I bought myself OMAP 3530 boards.Power-manger stuffs really difficult to use.When reading the TRMit is really confused me.
How DPLL1 and DPLL2 work with the OPP status?
There is two clock from outside system to DPLL1 power domain:DPLL1_ALWON_FCLK & DPLL1_FCLK.
As one can be used to as bypass clock and other as reference clock.
QUESTIONS:
1,When power-up (BOOT)which clock is used?from the x-load,I saw only DPLL1_ALWON_CLK from PRM.How to configure the clock path?
2,if at a certain time,both two clock from PRM & CM is input to DPLL1,which one will take effect?
3,How DPLL1 and DPLL2 work with the OPP status.
4,which clock can be accessed in bypass mode.what is low power bypass mode.
if any one knows the answer plz mail me"edwardlu666@hotmail.com" or left the remarks here.
thank you very much.
