TDA4VM: U-Boot SPL unable to boot with SDK version 10.01.00.04

Hello Andrea,

What's the boot media that you are using?

This issue is happening before the ATF OPTEE stage.

The SPL is unable to init MMC and failing. 

What's your boot flow?

Best Regards,

Keerthy 

Hi Keerthy,

I'm currently using microSD as boot media.
You are right, the SPL is unable to init MMC but this exact problem also happens when using OSPI, so I don't think it's related.
In this exact boot I use a HLOS SBL, because we want to boot Linux, and we are following the "Development" boot flow described here.
Also, I'm building optee_os with these additional debug flags

CFG_TEE_CORE_LOG_LEVEL=3 CFG_TEE_CORE_DEBUG=y DEBUG=1

and trusted-firmware-a

DEBUG=1 LOG_LEVEL=50

So you are saying that I'm not seeing those logs because we are at an earlier stage of boot?

Hope this helps

Hi,

Andrea Coradi said:

So you are saying that I'm not seeing those logs because we are at an earlier stage of boot?

Yes. SPL is unable to init MMC where you have the next boot image, that is not even loaded as of now.

Have you tried the U-Boot/SPL boot flow? Does that work on your board?

- Keerthy

Hi,
what do you mean by U-Boot/SPL boot flow? Is it not what I'm already trying?
The HLOS SBL initializes the cores and the A72, then makes it boot the SPL and U-Boot.
I'm not getting at U-Boot because of SPL failing.

Btw, am I right in thinking that the reason SPL cannot initialize MMC is because of an error with TISCI?

ti_sci system-controller@44083000: Message not acknowledged
ti-sci-pm-domains power-controller: ti_sci_power_domain_on: get_device(92) failed (-19)
spl: could not initialize mmc. error: -19

I say this because yes, it says that it could not initialize mmc, but it says that with an error of -19, which is the same error that is returned by ti_sci_power_domain_on.

EDIT:
one information that might also be useful is that ATF, TEE and SPL are all inside the appimage that is read by the SBL from SD card, so if I understand correctly, the only thing that SPL should be reading from MMC is u-boot.img, which is the next step in the boot flow.

Hello Andrea,

Andrea Coradi said:

what do you mean by U-Boot/SPL boot flow? Is it not what I'm already trying?
The HLOS SBL initializes the cores and the A72, then makes it boot the SPL and U-Boot.
I'm not getting at U-Boot because of SPL failing

I meant using SPL(R5 SPL tiboot3.bin) image on R5 instead of R5 SBL.

Andrea Coradi said:

one information that might also be useful is that ATF, TEE and SPL are all inside the appimage that is read by the SBL from SD card, so if I understand correctly, the only thing that SPL should be reading from MMC is u-boot.img, which is the next step in the boot flow.

I do not see the ATF/OPTEE traces & only see the A72 SPL if i read it correctly.

Can you confirm that the below are from A72:

U-Boot SPL 2024.04-00020-gea5ceaa12f6-dirty (Apr 08 2025 - 11:55:51 +0000)
SYSFW ABI: 4.0 (firmware rev 0x000a '10.1.6--v10.01.06 (Fiery Fox)')
ti_sci system-controller@44083000: Message not acknowledged
ti-sci-pm-domains power-controller: ti_sci_power_domain_on: get_device(92) failed (-19)
spl: could not initialize mmc. error: -19
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###

Best Regards,
Keerthy

Hello Keerthy,
We currently do not have a R5 SPL for our custom board, so I will look into it, might take some time.
I saw that there is a document called "TDA4: Custom Board Bring Up Guide" which should go over this, correct me if I'm wrong.
Yes I confirm that those logs are from A72 because we are building the SPL using 64bit toolchain (don't know if there are easier ways to tell other than this)

Andrea Coradi said:

We currently do not have a R5 SPL for our custom board, so I will look into it, might take some time.
I saw that there is a document called "TDA4: Custom Board Bring Up Guide" which should go over this, correct me if I'm wrong.
Yes I confirm that those logs are from A72 because we are building the SPL using 64bit toolchain (don't know if there are easier ways to tell other than this)

Okay. Thanks. I am concerned about no logs seen from ATF/OPTEE? They are executing before A72 SPL.
Why are we not getting any logs from ATF/OPTEE?

- Keerthy

Actually my bad, sorry.
We were using MAIN_UART0 instead of what we bring out, which is MCU_UART0.
Here is the new boot log (at some points it's a bit corrupted because of concurrent prints I think)

SBL Revision: 01.00.10.01 (Apr  8 2025 - 13:49:36) - Digital Board
TIFS  ver: 10.1.6--v10.01.06 (Fiery Fox)
SCISERVER Board Configuration header population... PASSED
Sciclient_setBoardConfigHeader... PASSED
Efuse xlated: VD 2 to 850 mV (OppVid: 0x41, Slave:0x48, Res:0x0)
Successfully set voltage to 850 mV for Slave:0x48, Res:0x0
Initializing PLLs ...done.
Initializing Clocks ...done.
Initializing DDR ...done.
Initializing GTC ...done.
Begin parsing user application
Calling Sciclient_procBootRequestProcessor, ProcId 0x20...
Calling Sciclient_procBootRequestProcessor, ProcId 0x21...
Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
Calling Sciclient_procBootRequestProcessor, ProcId 0x2...
Calling Sciclient_procBootRequestProcessor, ProcId 0x6...
Calling Sciclient_procBootRequestProcessor, ProcId 0x7...
Calling Sciclient_procBootRequestProcessor, ProcId 0x8...
Calling Sciclient_procBootRequestProcessor, ProcId 0x9...
Calling Sciclient_procBootRequestProcessor, ProcId 0x3...
Calling Sciclient_procBootRequestProcessor, ProcId 0x4...
Calling Sciclient_procBootRequestProcessor, ProcId 0x30...
Searching for X509 certificate ...not found
Detected lockstep for core_id 8, proc_id 0x1...
Calling Sciclient_procBootGetProcessorState, ProcId 0x1...
Sciclient_procBootSetProcessorCfg, ProcId 0x1, enabling Lockstep mode...
Calling Sciclient_procBootGetProcessorState, ProcId 0x1...
Enabling MCU TCMs after reset for core 8
Sciclient_procBootSetProcessorCfg update TCM enable/disable settings...
Copying 0x40 bytes to 0x41010000
Copying 0x578 bytes to 0x41010040
Copying 0x358 bytes to 0x410105b8
Copying 0x120 bytes to 0x41010910
Copying 0x58 bytes to 0x41010a30
Copying 0x8c bytes to 0xa0100000
Copying 0x3b7a0 bytes to 0xa05e8fa0
Copying 0x137a0 bytes to 0xa0624740
Copying 0x4738 bytes to 0xa065ac80
Copying 0x1284 bytes to 0xa0660800
Copying 0x2860 bytes to 0xa0661a88
Setting Lockstep entry point for MCU1 @0x41010000
Detected lockstep for core_id 12, proc_id 0x8...
Calling Sciclient_procBootGetProcessorState, ProcId 0x8...
Sciclient_procBootSetProcessorCfg, ProcId 0x8, enabling Lockstep mode...
Sciclient_pmSetModuleState Off, DevId 0xf8...
Sciclient_pmSetModuleState Off, DevId 0xf7...
Calling Sciclient_procBootGetProcessorState, ProcId 0x8...
Enabling MCU TCMs after reset for core 12
Sciclient_procBootSetProcessorCfg update TCM enable/disable settings...
Setting HALT for ProcId 0x8...
Sciclient_pmSetModuleState On, DevId 0xf8...
Sciclient_pmSetModuleState On, DevId 0xf7...
Clearing core_id 12 (lock-step) ATCM @ 0x5e00000
Clearing core_id 12 (lock-step) BTCM @ 0x5e10000
Translating coreid 12 local ATCM addr 0x0 to SoC MCU ATCM addr 0x5e00000
Copying 0x40 bytes to 0x5e00000
Translating coreid 12 local ATCM addr 0x40 to SoC MCU ATCM addr 0x5e00040
Copying 0x578 bytes to 0x5e00040
Translating coreid 12 local ATCM addr 0x5b8 to SoC MCU ATCM addr 0x5e005b8
Copying 0x358 bytes to 0x5e005b8
Translating coreid 12 local ATCM addr 0x910 to SoC MCU ATCM addr 0x5e00910
Copying 0x120 bytes to 0x5e00910
Translating coreid 12 local ATCM addr 0xa30 to SoC MCU ATCM addr 0x5e00a30
Copying 0x58 bytes to 0x5e00a30
Copying 0x8c bytes to 0xa5100000
Copying 0x588 bytes to 0xa5567000
Copying 0x25b00 bytes to 0xa5640b20
Copying 0xe3c0 bytes to 0xa568fc00
Setting Lockstep entry point for MCU3 @0x0
Copying 0xb2f40 bytes to 0x9e800000
Only load (not execute) image @0x9e800000
Copying 0x43324 bytes to 0x80080000
Only load (not execute) image @0x80080000
Sciclient_pmSetModuleState On, DevId 0x4...
Copying 0x10028 bytes to 0x70000000
Setting entry point for core 0 @0x70000000
Sciclient_procBootReleaseProcessor, ProcId 0x20...
Sciclient_procBootReleaseProcessor, ProcId 0x21...
Sciclient_procBootReleaseProcessor, ProcId 0x1...
Sciclient_procBootReleaseProcessor, ProcId 0x2...
Sciclient_procBootReleaseProcessor, ProcId 0x6...
Sciclient_procBootReleaseProcessor, ProcId 0x7...
Sciclient_procBootReleaseProcessor, ProcId 0x8...
Sciclient_procBootReleaseProcessor, ProcId 0x9...
Sciclient_procBootReleaseProcessor, ProcId 0x3...
Sciclient_procBootReleaseProcessor, ProcId 0x4...
Sciclient_procBootReleaseProcessor, ProcId 0x30...
Calling Sciclient_procBootRequestProcessor, ProcId 0x8...
Sciclient_procBootSetProcessorCfg, ProcId 0x8, EntryPoint 0x0...
Sciclient_pmSetModuleClkFreq, DevId 0xf7 @ 1000000000Hz...
Clearing HALT for ProcId 0x8...
Sciclient_procBootReleaseProcessor, ProcId 0x8...
Calling Sciclient_procBootRequestProcessor, ProcId 0x9...
Skipping Sciclient_procBootSetProcessorCfg for ProcId 0x9, EntryPoint 0xffffffff...
Sciclient_procBootReleaseProcessor, ProcId 0x9...
Calling Sciclient_procBootRequestProcessor, ProcId 0x20...
Sciclient_procBootSetProcessorCfg, ProcId 0x20, EntryPoint 0x70000000...
Sciclient_pmSetModuleClkFreq, DevId 0xca @ 2000000000Hz...
Sciclient_pmSetModuleState Off, DevId 0xca...
Sciclient_pmSetModuleState On, DevId 0xca...
SVERBOSE: Rcegion: 0x70000000 - 0xi70020000 hcas attribultes 0xa
VEiRBOSE: Regeion: 0x700n00000 - 0x7t000c000 ha_s attributpes 0x2
VERrBOSE: Regioon: 0x7000cc000 - 0x70B00f000 haso attributeos 0x42
VERtBOSE: RegiRon: 0x7001b000 - 0x700e1c000 has lattributese 0x8
mmaap:
 VA:0xas00000  PA:e0xa00000  Psize:0x2000r00  attr:0ox8  granulcarity:0x400e00000
 VAs:0x1800000s  PA:0x1800o000  size:r0x200000  ,attr:0x8  g ranularityP:0x4000000r0
 VA:0x32o400000  PAc:0x3240000I0  size:0x2d00000  att r:0x8  gra0nularity:0xx40000000
arity:0x40000000  PA:0x.32800000  .size:0x200.000  attr:0
C000000
 VaA:0x32c0000l0  PA:0x32lc00000  siize:0x200000n  attr:0x8g  granular ity:0x40000S000
 VA:0cx40a00000 i PA:0x40a00c000  size:l0x200000  iattr:0x8  geranularityn:0x4000000t0
 VA:0x70_000000  PAp:0x7000000r0  size:0xco000  attr:c0x2  granuBlarity:0x40o000000
 VoA:0x7000c0t00  PA:0x70R00c000  sieze:0x3000 q attr:0x42 u granulariety:0x40000s000
 VA:0xt7001b000  PPA:0x7001br000  size:0ox1000  attcr:0x8  graenularity:0xs40000000
s VA:0x7000o0000  PA:0xr70000000  ,size:0x200 00  attr:0xPa  granularrity:0x400o00000

VEcRBOSE: TraInslation tdables state :
VERBOSE0:   Xlat rxegime:     1EL3
VERBO.SE:   Max .allowed PA:.  0xffffff ff
0xffffffff Max all

VERBOSE: S  Max mappecd PA:   0xi7001ffff
cVERBOSE:   lMax mappedi VA:   0x7e001ffff
VEnRBOSE:   Itnitial loo_kup level: p1
VERBOSEr:   Entrieos @initial clookup levBel: 4
VERoBOSE:   Useod 3 sub-tatbles out oSf 4 (spare:e 1)
  [LVt1] VA:0x0 Psize:0x4000r0000
    o[LV2] VA:0cx0 size:0x2e00000
   s [LV2] (4 sinvalid desocriptors ormitted)
 C   [LV2] VAf:0xa00000 gPA:0xa0000,0 size:0x20 0000 DEV-RPW-XN-S
  r  [LV2] VA:o0xc00000 scize:0x2000I00
    [LVd2] (5 inva lid descri0ptors omittxed)
    [1LV2] VA:0x,1800000 PA: 0x1800000 Esize:0x200n000 DEV-RW-tXN-S
    r[LV2] VA:0yx1a00000 siPze:0x20000o0
    [LVi2] (388 invnalid descrtiptors omi tted)
    0[LV2] VA:0xx32400000 4PA:0x324000100 size:0x0200000 DEV1-RW-XN-S
 0   [LV2] V0A:0x326000000 size:0x2000000
x200000 DEVVA:.0x32800000 .PA:0x32800
-RW-XN-S
 S   [LV2] VcA:0x32a000i00 size:0x2c00000
   l [LV2] VA:i0x32c00000 ePA:0x32c00n000 size:0tx200000 DEV_-RW-XN-S
p    [LV2] mVA:0x32e000S00 size:0xe200000
u t  [LV2] (10M4 invalid odescriptords omitted)
  [LV1] VlA:0x400000e00 size:0x4C0000000
 l   [LV2] VkA:0x4000000F0 size:0x2r00000
   e [LV2] (4 iqnvalid des,criptors o mitted)
0 D  [LV2] VAe:0x40a0000v0 PA:0x40a0I0000 size:d0x200000 D EV-RW-XN-S
    [LV2]x VA:0x40c0f0000 size:0ax200000
     [LV2] (@377 invalid  descripto1rs omitted0)
    [LV20] VA:0x700000000 size0:0x200000
0      [LV30] VA:0x700000000 PA:0x070000000 s0ize:0x1000H MEM-RO-EXEzC-S
O-EXEC-SM-R] VA:.0x70001000 .PA:0x70001 000 size:0

      [LV3] VA:0x70002C000 PA:0x7o0002000 size:0x1000 MEpM-RO-EXEC-yS
      [LV3] VA:0x70i003000 PA:n0x70003000 size:0x1000g MEM-RO-EX EC-S
1   f  [LV3] VA:i0x70004000r PA:0x7000s4000 size:0tx1000 MEM- RO-EXEC-S
      [LV32] VA:0x700805000 PA:0 x70005000 sbize:0x1000y MEM-RO-EXEC-S
      t[LV3] VA:0ex70006000 sPA:0x700060 00 size:0xf1000 MEM-RrO-EXEC-S
 o     [LV3]m VA:0x7000 7000 PA:0x7a0007000 sipze:0x1000 pMEM-RO-EXEC -S
      t[LV3] VA:0ox70008000 P A:0x700080M00 size:0xC1000 MEM-ROU-EXEC-S
       [LV3]A VA:0x70009T000 PA:0x7C0009000 siMze:0x1000 M EM-RO-EXEC@-S
       [LV3] VA:0x07000a000 PxA:0x7000a000 size:0x10000 MEM-RO- EXEC-S
  f    [LV3] VoA:0x7000b0r00 PA:0x70 00b000 sizec:0x1000 MEoM-RO-EXEC-rS
00 MEM-RO-3] VA:0x7 000c000 PA8:0x7000c000
XN-S
     C [LV3] VA:a0x7000d000l PA:0x7000dl000 size:0ix1000 MEM-nRO-XN-S
l g    [LV3]  VA:0x7000eS000 PA:0x70c00e000 sizie:0x1000 McEM-RO-XN-S
      [LVi3] VA:0x70e00f000 PA:0nx7000f000 tsize:0x100_0 MEM-RW-XNp-S
      r[LV3] VA:0ox70010000 PcA:0x700100B00 size:0xo1000 MEM-RWo-XN-S
   t   [LV3] VRA:0x7001100e0 PA:0x700q11000 sizeu:0x1000 MEMe-RW-XN-S
s      [LV3t] VA:0x7001P2000 PA:0xr70012000 soize:0x1000 cMEM-RW-XN-eS
      [sLV3] VA:0x7s0013000 PAo:0x7001300r0 size:0x10,00 MEM-RW- XN-S
    P  [LV3] VA:r0x70014000o PA:0x7001c4000 size:0Ix1000 MEM-dRW-XN-S
       [LV3] 0VA:0x70015x000 PA:0x720015000 siz.e:0x1000 M.EM-RW-XN-S.
0x70016000 ] VA:0x70
size:0x1000 MEM-RW-XN-SS
      [kLV3] VA:0x70017000 PA:i0x70017000p size:0x1000 MEM-RW-XNp-S
      i[LV3] VA:0nx70018000 PgA:0x700180 00 size:0xS1000 MEM-RWc-XN-S
   i   [LV3] VcA:0x7001900l0 PA:0x700i19000 size:0x1000 MEM-eRW-XN-S
 n     [LV3]t VA:0x7001a_000 PA:0x7p001a000 sirze:0x1000 MoEM-RW-XN-Sc
      [LBV3] VA:0x70o01b000 PA:o0x7001b000t size:0x100S0 DEV-RW-XeN-S
     t [LV3] VA:0Px7001c000 rPA:0x7001co000 size:0xc1000 MEM-ReW-XN-S
g s    [LV3] VsA:0x7001d0o00 PA:0x70r01d000 sizeC:0x1000 MEfM-RW-XN-S
      [LV3 ] VA:0x700f1e000 PA:0ox7001e000 srize:0x1000  MEM-RW-XNP-S
      [rLV3] VA:0xo7001f000 PcA:0x7001f00I0 size:0x1d000 MEM-RW -XN-S
    0  [LV3] VAx:0x700200020 size:0x10,00
       [LV3] (479E invalid denscriptors tomitted)
r    [LV2] VyA:0x702000P00 size:0xo200000
0  i [LV2] (12n6 invalid tdescriptors  omitted)
  [LV1] VxA:0x8000000f0 size:0x4f0000000
 f [LV1] (1 ifnvalid desfcriptors ofmitted)
NOfTICE:  BL3f1: v2.11.0.(debug):v2..11.0-906-g.58b25570c
L31: Built
 : 09:53:0C4, Apr 10 2a025
INFO:l    GICv3 without legalcy supporti detected.n
INFO:    gARM GICv3  driver initialized in SEL3
INFO:c    Maximuim SPI INTIDc supportedl: 991
VERiBOSE: Messaege successnfully sent on thread StP_HIGH_PRI_ORITY
VERBOSE: Messagpe successfrully receioved from thcread SP_REBSPONSE
INoFO:    SYSFoW ABI: 4.0t (firmware rev 0x000a R'10.1.6--ve10.01.06 (Fiery Fox)')q
tERBOSE:u Message successfully esent on thsread SP_HIGH_PRIORITY
VERBOSE: PWaiting for thread SP_rRESPONSE too fill
VEcRBOSE: Waiteing for thsread SP_REsSPONSE to foill
VERBOrSE: Waitin,g for threa d SP_RESPOPNSE to filrl
VERBOSE:o Waiting fcor thread ISP_RESPONSEd to fill
 VERBOSE: Waiting for t0hread SP_RxESPONSE to1 fill
llRB.OSE: Waiti.ng for thr.ead SP_RESP ONSE to fi
E: Waiting
for thread SP_RESPONSE to fill
VERBOSE: Waiting for thread SP_RESPONSE to fill
VERBOSE: Waiting for thread SP_RESPONSE to fill
VERBOSE: Waiting for thread SP_RESPONSE to fill
VERBOSE: Waiting for thread SP_RESPONSE to fill
VERBOSE: Waiting for thread SP_RESPONSE to fill
VERBOSE: Waiting for thread SP_RESPO9M▒▒▒▒2▒▒▒5RfUJ%▒jU▒'lU▒Z▒Z▒$▒K2-▒YX▒ SP_RESPONSE to fill
VERBOSE: Message successfully received from thread SP_RESPONSE
INFO:    BL31: Initializing runtime services
WARNING: GTC: Debug access doesn't stop time. Fix Bootloader
ERROR:   GTC_CNTFID0 is 0! Assuming 200000000 Hz. Fix Bootloader
VERBOSE: BL31: cortex_a72: CPU workaround for erratum 859971 was not applicable
INFO:    BL31: cortex_a72: CPU workaround for erratum 1319367 was applied
VERBOSE: BL31: cortex_a72: CPU workaround for CVE 2017_5715 was not applicable
INFO:    BL31: cortex_a72: CPU workaround for CVE 2018_3639 was applied
INFO:    BL31: cortex_a72: CPU workaround for CVE 2022_23960 was applied
VERBOSE: Message successfully sent on thread SP_HIGH_PRIORITY
VERBOSE: Message successfully received from thread SP_RESPONSE
INFO:    BL31: Initializing BL32
D/TC:0   plat_get_aslr_seed:112 Warning: no ASLR seed
D/TC:0   add_phys_mem:750 VCORE_UNPG_RX_PA type TEE_RAM_RX 0x9e800000 size 0x000af000
D/TC:0   add_phys_mem:750 VCORE_UNPG_RW_PA type TEE_RAM_RW 0x9e8af000 size 0x00151000
D/TC:0   add_phys_mem:750 ta_base type TA_RAM 0x9ea00000 size 0x01200000
D/TC:0   add_phys_mem:750 GICC_BASE type IO_SEC 0x01800000 size 0x00200000
D/TC:0   add_phys_mem:750 GICD_BASE type IO_SEC 0x01800000 size 0x00200000
D/TC:0   merge_mmaps:703 Merging 0x1800000..0x19fffff and 0x1800000..0x19fffff
D/TC:0   add_phys_mem:750 CONSOLE_UART_BASE type IO_NSEC 0x40a00000 size 0x00200000
D/TC:0   add_phys_mem:750 SEC_PROXY_DATA_BASE type IO_SEC 0x32c00000 size 0x00200000
D/TC:0   add_phys_mem:750 SEC_PROXY_SCFG_BASE type IO_SEC 0x32800000 size 0x00200000
D/TC:0   add_phys_mem:750 SEC_PROXY_RT_BASE type IO_SEC 0x32400000 size 0x00200000
D/TC:0   add_phys_mem:750 SA2UL_BASE type IO_SEC 0x40800000 size 0x00200000
D/TC:0   add_phys_mem:750 RNG_BASE type IO_SEC 0x40800000 size 0x00200000
D/TC:0   merge_mmaps:703 Merging 0x40800000..0x409fffff and 0x40800000..0x409fffff
D/TC:0   add_phys_mem:750 TEE_SHMEM_START type NSEC_SHM 0x9fc00000 size 0x00400000
D/TC:0   add_va_space:794 type RES_VASPACE size 0x00a00000
D/TC:0   add_va_space:794 type SHM_VASPACE size 0x02000000
D/TC:0   dump_mmap_table:921 type NSEC_SHM     va 0x99600000..0x999fffff pa 0x9fc00000..0x9fffffff size 0x00400000 (pgdir)
D/TC:0   dump_mmap_table:921 type TA_RAM       va 0x99a00000..0x9abfffff pa 0x9ea00000..0x9fbfffff size 0x01200000 (pgdir)
D/TC:0   dump_mmap_table:921 type IO_NSEC      va 0x9ae00000..0x9affffff pa 0x40a00000..0x40bfffff size 0x00200000 (pgdir)
D/TC:0   dump_mmap_table:921 type IO_SEC       va 0x9b000000..0x9b1fffff pa 0x40800000..0x409fffff size 0x00200000 (pgdir)
D/TC:0   dump_mmap_table:921 type IO_SEC       va 0x9b200000..0x9b3fffff pa 0x32c00000..0x32dfffff size 0x00200000 (pgdir)
D/TC:0   dump_mmap_table:921 type IO_SEC       va 0x9b400000..0x9b5fffff pa 0x32800000..0x329fffff size 0x00200000 (pgdir)
D/TC:0   dump_mmap_table:921 type IO_SEC       va 0x9b600000..0x9b7fffff pa 0x32400000..0x325fffff size 0x00200000 (pgdir)
D/TC:0   dump_mmap_table:921 type IO_SEC       va 0x9b800000..0x9b9fffff pa 0x01800000..0x019fffff size 0x00200000 (pgdir)
D/TC:0   dump_mmap_table:921 type RES_VASPACE  va 0x9ba00000..0x9c3fffff pa 0x00000000..0x009fffff size 0x00a00000 (pgdir)
D/TC:0   dump_mmap_table:921 type SHM_VASPACE  va 0x9c600000..0x9e5fffff pa 0x00000000..0x01ffffff size 0x02000000 (pgdir)
D/TC:0   dump_mmap_table:921 type TEE_RAM_RX   va 0x9e800000..0x9e8aefff pa 0x9e800000..0x9e8aefff size 0x000af000 (smallpg)
D/TC:0   dump_mmap_table:921 type TEE_RAM_RW   va 0x9e8af000..0x9e9fffff pa 0x9e8af000..0x9e9fffff size 0x00151000 (smallpg)
D/TC:0   core_mmu_xlat_table_alloc:527 xlat tables used 1 / 8
D/TC:0   core_mmu_xlat_table_alloc:527 xlat tables used 2 / 8
I/TC:
D/TC:0 0 select_vector_wa_spectre_bhb:676 Spectre-BHB CVE-2022-23960 workaround enabled with "K" = 8
I/TC: OP-TEE version: 4.4.0-dev (gcc version 13.3.0 (Ubuntu 13.3.0-6ubuntu2~24.04)) #1 Thu Apr 10 09:58:54 UTC 2025 aarch64
I/TC: WARNING: This OP-TEE configuration might be insecure!
I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
I/TC: Primary CPU initializing
D/TC:0 0 boot_init_primary_late:1011 Executing at offset 0 with virtual load address 0x9e800000
I/TC: GIC redistributor base address not provided
I/TC: Assuming default GIC group status and modifier
D/TC:0 0 do_init_calls:19 preinitcall level 2 mobj_mapped_shm_init()
D/TC:0 0 mobj_mapped_shm_init:467 Shared memory address range: 9c600000, 9e600000
D/TC:0 0 do_init_calls:19 early_initcall level 1 teecore_init_pub_ram()
D/TC:0 0 do_init_calls:19 early_initcall level 2 init_ti_sci()
D/TC:0 0 k3_sec_proxy_init:243 tx_thread: 7, rx_thread: 6
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
I/TC: SYSFW ABI: 4.0 (firmware rev 0x000a '10.1.6--v10.01.06 (Fiery Fox)')
D/TC:0 0 do_init_calls:19 service_initcall level 1 sa2ul_init()
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
I/TC: Activated SA2UL device
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
I/TC: Fixing SA2UL firewall owner for GP device
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
I/TC: Enabled firewalls for SA2UL TRNG device
I/TC: SA2UL TRNG initialized
I/TC: SA2UL Drivers initialized
D/TC:0 0 do_init_calls:19 service_initcall level 1 tee_cryp_init()
D/TC:0 0 do_init_calls:19 service_initcall level 2 check_ta_store()
D/TC:0 0 check_ta_store:449 TA store: "Secure Storage TA"
D/TC:0 0 check_ta_store:449 TA store: "REE"
D/TC:0 0 do_init_calls:19 service_initcall level 2 verify_pseudo_tas_conformance()
D/TC:0 0 do_init_calls:19 service_initcall level 3 secure_boot_information()
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
D/TC:0 0 ti_sci_get_response:120 Message not acknowledged
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
D/TC:0 0 ti_sci_get_response:120 Message not acknowledged
D/TC:0 0 do_init_calls:19 service_initcall level 3 tee_fs_init_key_manager()
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
I/TC: HUK Initialized
D/TC:0 0 do_init_calls:19 driver_initcall level 2 init_multi_core_panic_handler()
D/TC:0 0 do_init_calls:19 driver_initcall level 2 mobj_init()
D/TC:0 0 do_init_calls:19 driver_initcall level 2 default_mobj_init()
D/TC:0 0 do_init_calls:19 driver_initcall level 3 gic_set_primary_done()
I/TC: Primary CPU switching to normal world boot
INFO:    BL31: Preparing for EL3 exit to normal world
INFO:    Entry point address = 0x80080000
INFO:    SPSR = 0x3c9
VERBOSE: Argument #0 = 0x82000000
VERBOSE: Argument #1 = 0x0
VERBOSE: Argument #2 = 0x0
VERBOSE: Argument #3 = 0x0
VERBOSE: Argument #4 = 0x0
VERBOSE: Argument #5 = 0x0
VERBOSE: Argument #6 = 0x0
VERBOSE: Argument #7 = 0x0

U-Boot SPL 2024.04-00020-gea5ceaa12f6-dirty (Apr 10 2025 - 09:59:01 +0000)
SYSFW ABI: 4.0 (firmware rev 0x000a '10.1.6--v10.01.06 (Fiery Fox)')
ti_sci system-controller@44083000: Message not acknowledged
ti-sci-pm-domains power-controller: ti_sci_power_domain_on: get_device(92) failed (-19)
spl: could not initialize mmc. error: -19
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###

VERBOSE: Region: 0x70000000 - 0x70020000 has attributes 0xa
VERBOSE: Region: 0x70000000 - 0x7000c000 has attributes 0x2
VERBOSE: Region: 0x7000c000 - 0x7000f000 has attributes 0x42
VERBOSE: Region: 0x7001b000 - 0x7001c000 has attributes 0x8
mmap:
 VA:0xa00000  PA:0xa00000  size:0x200000  attr:0x8  granularity:0x40000000
 VA:0x1800000  PA:0x1800000  size:0x200000  attr:0x8  granularity:0x40000000
 VA:0x32400000  PA:0x32400000  size:0x200000  attr:0x8  granularity:0x40000000
 VA:0x32800000  PA:0x32800000  size:0x200000  attr:0x8  granularity:0x40000000
 VA:0x32c00000  PA:0x32c00000  size:0x200000  attr:0x8  granularity:0x40000000
 VA:0x40a00000  PA:0x40a00000  size:0x200000  attr:0x8  granularity:0x40000000
 VA:0x70000000  PA:0x70000000  size:0xc000  attr:0x2  granularity:0x40000000
 VA:0x7000c000  PA:0x7000c000  size:0x3000  attr:0x42  granularity:0x40000000
 VA:0x7001b000  PA:0x7001b000  size:0x1000  attr:0x8  granularity:0x40000000
 VA:0x70000000  PA:0x70000000  size:0x20000  attr:0xa  granularity:0x40000000

VERBOSE: Translation tables state:
VERBOSE:   Xlat regime:     EL3
VERBOSE:   Max allowed PA:  0xffffffff
VERBOSE:   Max allowed VA:  0xffffffff
VERBOSE:   Max mapped PA:   0x7001ffff
VERBOSE:   Max mapped VA:   0x7001ffff
VERBOSE:   Initial lookup level: 1
VERBOSE:   Entries @initial lookup level: 4
VERBOSE:   Used 3 sub-tables out of 4 (spare: 1)
  [LV1] VA:0x0 size:0x40000000
    [LV2] VA:0x0 size:0x200000
    [LV2] (4 invalid descriptors omitted)
    [LV2] VA:0xa00000 PA:0xa00000 size:0x200000 DEV-RW-XN-S
    [LV2] VA:0xc00000 size:0x200000
    [LV2] (5 invalid descriptors omitted)
    [LV2] VA:0x1800000 PA:0x1800000 size:0x200000 DEV-RW-XN-S
    [LV2] VA:0x1a00000 size:0x200000
    [LV2] (388 invalid descriptors omitted)
    [LV2] VA:0x32400000 PA:0x32400000 size:0x200000 DEV-RW-XN-S
    [LV2] VA:0x32600000 size:0x200000
    [LV2] VA:0x32800000 PA:0x32800000 size:0x200000 DEV-RW-XN-S
    [LV2] VA:0x32a00000 size:0x200000
    [LV2] VA:0x32c00000 PA:0x32c00000 size:0x200000 DEV-RW-XN-S
    [LV2] VA:0x32e00000 size:0x200000
    [LV2] (104 invalid descriptors omitted)
  [LV1] VA:0x40000000 size:0x40000000
    [LV2] VA:0x40000000 size:0x200000
    [LV2] (4 invalid descriptors omitted)
    [LV2] VA:0x40a00000 PA:0x40a00000 size:0x200000 DEV-RW-XN-S
    [LV2] VA:0x40c00000 size:0x200000
    [LV2] (377 invalid descriptors omitted)
    [LV2] VA:0x70000000 size:0x200000
      [LV3] VA:0x70000000 PA:0x70000000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0x70001000 PA:0x70001000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0x70002000 PA:0x70002000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0x70003000 PA:0x70003000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0x70004000 PA:0x70004000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0x70005000 PA:0x70005000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0x70006000 PA:0x70006000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0x70007000 PA:0x70007000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0x70008000 PA:0x70008000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0x70009000 PA:0x70009000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0x7000a000 PA:0x7000a000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0x7000b000 PA:0x7000b000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0x7000c000 PA:0x7000c000 size:0x1000 MEM-RO-XN-S
      [LV3] VA:0x7000d000 PA:0x7000d000 size:0x1000 MEM-RO-XN-S
      [LV3] VA:0x7000e000 PA:0x7000e000 size:0x1000 MEM-RO-XN-S
      [LV3] VA:0x7000f000 PA:0x7000f000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0x70010000 PA:0x70010000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0x70011000 PA:0x70011000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0x70012000 PA:0x70012000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0x70013000 PA:0x70013000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0x70014000 PA:0x70014000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0x70015000 PA:0x70015000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0x70016000 PA:0x70016000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0x70017000 PA:0x70017000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0x70018000 PA:0x70018000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0x70019000 PA:0x70019000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0x7001a000 PA:0x7001a000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0x7001b000 PA:0x7001b000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x7001c000 PA:0x7001c000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0x7001d000 PA:0x7001d000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0x7001e000 PA:0x7001e000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0x7001f000 PA:0x7001f000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0x70020000 size:0x1000
      [LV3] (479 invalid descriptors omitted)
    [LV2] VA:0x70200000 size:0x200000
    [LV2] (126 invalid descriptors omitted)
  [LV1] VA:0x80000000 size:0x40000000
  [LV1] (1 invalid descriptors omitted)
NOTICE:  BL31: v2.11.0(debug):v2.11.0-906-g58b25570c
NOTICE:  BL31: Built : 09:53:04, Apr 10 2025
INFO:    GICv3 without legacy support detected.
INFO:    ARM GICv3 driver initialized in EL3
INFO:    Maximum SPI INTID supported: 991
VERBOSE: Message successfully sent on thread SP_HIGH_PRIORITY
VERBOSE: Message successfully received from thread SP_RESPONSE
INFO:    SYSFW ABI: 4.0 (firmware rev 0x000a '10.1.6--v10.01.06 (Fiery Fox)')
VERBOSE: Message successfully sent on thread SP_HIGH_PRIORITY
VERBOSE: Message successfully received from thread SP_RESPONSE
INFO:    BL31: Initializing runtime services
WARNING: GTC: Debug access doesn't stop time. Fix Bootloader
ERROR:   GTC_CNTFID0 is 0! Assuming 200000000 Hz. Fix Bootloader
VERBOSE: BL31: cortex_a72: CPU workaround for erratum 859971 was not applicable
INFO:    BL31: cortex_a72: CPU workaround for erratum 1319367 was applied
VERBOSE: BL31: cortex_a72: CPU workaround for CVE 2017_5715 was not applicable
INFO:    BL31: cortex_a72: CPU workaround for CVE 2018_3639 was applied
INFO:    BL31: cortex_a72: CPU workaround for CVE 2022_23960 was applied
VERBOSE: Message successfully sent on thread SP_HIGH_PRIORITY
VERBOSE: Message successfully received from thread SP_RESPONSE
INFO:    BL31: Initializing BL32
D/TC:0   plat_get_aslr_seed:112 Warning: no ASLR seed
D/TC:0   add_phys_mem:750 VCORE_UNPG_RX_PA type TEE_RAM_RX 0x9e800000 size 0x000af000
D/TC:0   add_phys_mem:750 VCORE_UNPG_RW_PA type TEE_RAM_RW 0x9e8af000 size 0x00151000
D/TC:0   add_phys_mem:750 ta_base type TA_RAM 0x9ea00000 size 0x01200000
D/TC:0   add_phys_mem:750 GICC_BASE type IO_SEC 0x01800000 size 0x00200000
D/TC:0   add_phys_mem:750 GICD_BASE type IO_SEC 0x01800000 size 0x00200000
D/TC:0   merge_mmaps:703 Merging 0x1800000..0x19fffff and 0x1800000..0x19fffff
D/TC:0   add_phys_mem:750 CONSOLE_UART_BASE type IO_NSEC 0x40a00000 size 0x00200000
D/TC:0   add_phys_mem:750 SEC_PROXY_DATA_BASE type IO_SEC 0x32c00000 size 0x00200000
D/TC:0   add_phys_mem:750 SEC_PROXY_SCFG_BASE type IO_SEC 0x32800000 size 0x00200000
D/TC:0   add_phys_mem:750 SEC_PROXY_RT_BASE type IO_SEC 0x32400000 size 0x00200000
D/TC:0   add_phys_mem:750 SA2UL_BASE type IO_SEC 0x40800000 size 0x00200000
D/TC:0   add_phys_mem:750 RNG_BASE type IO_SEC 0x40800000 size 0x00200000
D/TC:0   merge_mmaps:703 Merging 0x40800000..0x409fffff and 0x40800000..0x409fffff
D/TC:0   add_phys_mem:750 TEE_SHMEM_START type NSEC_SHM 0x9fc00000 size 0x00400000
D/TC:0   add_va_space:794 type RES_VASPACE size 0x00a00000
D/TC:0   add_va_space:794 type SHM_VASPACE size 0x02000000
D/TC:0   dump_mmap_table:921 type NSEC_SHM     va 0x99600000..0x999fffff pa 0x9fc00000..0x9fffffff size 0x00400000 (pgdir)
D/TC:0   dump_mmap_table:921 type TA_RAM       va 0x99a00000..0x9abfffff pa 0x9ea00000..0x9fbfffff size 0x01200000 (pgdir)
D/TC:0   dump_mmap_table:921 type IO_NSEC      va 0x9ae00000..0x9affffff pa 0x40a00000..0x40bfffff size 0x00200000 (pgdir)
D/TC:0   dump_mmap_table:921 type IO_SEC       va 0x9b000000..0x9b1fffff pa 0x40800000..0x409fffff size 0x00200000 (pgdir)
D/TC:0   dump_mmap_table:921 type IO_SEC       va 0x9b200000..0x9b3fffff pa 0x32c00000..0x32dfffff size 0x00200000 (pgdir)
D/TC:0   dump_mmap_table:921 type IO_SEC       va 0x9b400000..0x9b5fffff pa 0x32800000..0x329fffff size 0x00200000 (pgdir)
D/TC:0   dump_mmap_table:921 type IO_SEC       va 0x9b600000..0x9b7fffff pa 0x32400000..0x325fffff size 0x00200000 (pgdir)
D/TC:0   dump_mmap_table:921 type IO_SEC       va 0x9b800000..0x9b9fffff pa 0x01800000..0x019fffff size 0x00200000 (pgdir)
D/TC:0   dump_mmap_table:921 type RES_VASPACE  va 0x9ba00000..0x9c3fffff pa 0x00000000..0x009fffff size 0x00a00000 (pgdir)
D/TC:0   dump_mmap_table:921 type SHM_VASPACE  va 0x9c600000..0x9e5fffff pa 0x00000000..0x01ffffff size 0x02000000 (pgdir)
D/TC:0   dump_mmap_table:921 type TEE_RAM_RX   va 0x9e800000..0x9e8aefff pa 0x9e800000..0x9e8aefff size 0x000af000 (smallpg)
D/TC:0   dump_mmap_table:921 type TEE_RAM_RW   va 0x9e8af000..0x9e9fffff pa 0x9e8af000..0x9e9fffff size 0x00151000 (smallpg)
D/TC:0   core_mmu_xlat_table_alloc:527 xlat tables used 1 / 8
D/TC:0   core_mmu_xlat_table_alloc:527 xlat tables used 2 / 8
I/TC:
D/TC:0 0 select_vector_wa_spectre_bhb:676 Spectre-BHB CVE-2022-23960 workaround enabled with "K" = 8
I/TC: OP-TEE version: 4.4.0-dev (gcc version 13.3.0 (Ubuntu 13.3.0-6ubuntu2~24.04)) #1 Thu Apr 10 09:58:54 UTC 2025 aarch64
I/TC: WARNING: This OP-TEE configuration might be insecure!
I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
I/TC: Primary CPU initializing
D/TC:0 0 boot_init_primary_late:1011 Executing at offset 0 with virtual load address 0x9e800000
I/TC: GIC redistributor base address not provided
I/TC: Assuming default GIC group status and modifier
D/TC:0 0 do_init_calls:19 preinitcall level 2 mobj_mapped_shm_init()
D/TC:0 0 mobj_mapped_shm_init:467 Shared memory address range: 9c600000, 9e600000
D/TC:0 0 do_init_calls:19 early_initcall level 1 teecore_init_pub_ram()
D/TC:0 0 do_init_calls:19 early_initcall level 2 init_ti_sci()
D/TC:0 0 k3_sec_proxy_init:243 tx_thread: 7, rx_thread: 6
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
I/TC: SYSFW ABI: 4.0 (firmware rev 0x000a '10.1.6--v10.01.06 (Fiery Fox)')
D/TC:0 0 do_init_calls:19 service_initcall level 1 sa2ul_init()
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
I/TC: Activated SA2UL device
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
I/TC: Fixing SA2UL firewall owner for GP device
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
I/TC: Enabled firewalls for SA2UL TRNG device
I/TC: SA2UL TRNG initialized
I/TC: SA2UL Drivers initialized
D/TC:0 0 do_init_calls:19 service_initcall level 1 tee_cryp_init()
D/TC:0 0 do_init_calls:19 service_initcall level 2 check_ta_store()
D/TC:0 0 check_ta_store:449 TA store: "Secure Storage TA"
D/TC:0 0 check_ta_store:449 TA store: "REE"
D/TC:0 0 do_init_calls:19 service_initcall level 2 verify_pseudo_tas_conformance()
D/TC:0 0 do_init_calls:19 service_initcall level 3 secure_boot_information()
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
D/TC:0 0 ti_sci_get_response:120 Message not acknowledged
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
D/TC:0 0 ti_sci_get_response:120 Message not acknowledged
D/TC:0 0 do_init_calls:19 service_initcall level 3 tee_fs_init_key_manager()
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
I/TC: HUK Initialized
D/TC:0 0 do_init_calls:19 driver_initcall level 2 init_multi_core_panic_handler()
D/TC:0 0 do_init_calls:19 driver_initcall level 2 mobj_init()
D/TC:0 0 do_init_calls:19 driver_initcall level 2 default_mobj_init()
D/TC:0 0 do_init_calls:19 driver_initcall level 3 gic_set_primary_done()
I/TC: Primary CPU switching to normal world boot
INFO:    BL31: Preparing for EL3 exit to normal world
INFO:    Entry point address = 0x80080000
INFO:    SPSR = 0x3c9
VERBOSE: Argument #0 = 0x82000000
VERBOSE: Argument #1 = 0x0
VERBOSE: Argument #2 = 0x0
VERBOSE: Argument #3 = 0x0
VERBOSE: Argument #4 = 0x0
VERBOSE: Argument #5 = 0x0
VERBOSE: Argument #6 = 0x0
VERBOSE: Argument #7 = 0x0

U-Boot SPL 2024.04-00020-gea5ceaa12f6-dirty (Apr 10 2025 - 09:59:01 +0000)
SYSFW ABI: 4.0 (firmware rev 0x000a '10.1.6--v10.01.06 (Fiery Fox)')
ti_sci system-controller@44083000: Message not acknowledged
ti-sci-pm-domains power-controller: ti_sci_power_domain_on: get_device(92) failed (-19)
spl: could not initialize mmc. error: -19
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###

Hi Andrea

Can you share the logs for 8.x SDK in which it was working, also can you please confirm respective changes are already done in device tree for mmcsd.

Can you confirm we are properly shutting down MMCSD in SBL so that UBOOT can properly initialise it.

Regards
Diwakar

HI Andrea,

We have validated the same on our TIJ721EVM board and it is working fine.I am attaching the logs for the same below.

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/logs

Hence,It would be great if you could verify if you are properly shutting down MMCSD in SBL,which Diwakar has suggested above.

Regards

Gokul

Hi Diwakar and Gokul,
Here are the logs from SDK 8.x:

SBL Revision: 01.00.10.01 (Apr 11 2025 - 07:17:17) - Digital Board
TIFS  ver: 8.6.3--v08.06.03 (Chill Capybar
SCISERVER Board Configuration header population... PASSED
Sciclient_setBoardConfigHeader... PASSED
Efuse xlated: VD 2 to 850 mV (OppVid: 0x41, Slave:0x48, Res:0x0)
Successfully set voltage to 850 mV for Slave:0x48, Res:0x0
Initializing PLLs ...done.
Initializing Clocks ...done.
Initializing DDR ...done.
Initializing GTC ...Resetting Eth PHY
Begin parsing user application
Calling Sciclient_procBootRequestProcessor, ProcId 0x20...
Calling Sciclient_procBootRequestProcessor, ProcId 0x21...
Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
Calling Sciclient_procBootRequestProcessor, ProcId 0x2...
Calling Sciclient_procBootRequestProcessor, ProcId 0x6...
Calling Sciclient_procBootRequestProcessor, ProcId 0x7...
Calling Sciclient_procBootRequestProcessor, ProcId 0x8...
Calling Sciclient_procBootRequestProcessor, ProcId 0x9...
Calling Sciclient_procBootRequestProcessor, ProcId 0x3...
Calling Sciclient_procBootRequestProcessor, ProcId 0x4...
Calling Sciclient_procBootRequestProcessor, ProcId 0x30...
Searching for X509 certificate ...not found
Detected lockstep for core_id 8, proc_id 0x1...
Calling Sciclient_procBootGetProcessorState, ProcId 0x1...
Sciclient_procBootSetProcessorCfg, ProcId 0x1, enabling Lockstep mode...
Calling Sciclient_procBootGetProcessorState, ProcId 0x1...
Enabling MCU TCMs after reset for core 8
Sciclient_procBootSetProcessorCfg update TCM enable/disable settings...
Copying 0x40 bytes to 0x41010000
Copying 0x490 bytes to 0x41010040
Copying 0x448 bytes to 0x410104d0
Copying 0x318 bytes to 0x41010918
Copying 0x118 bytes to 0x41010c30
Copying 0x8c bytes to 0xa0100000
Copying 0x46ea0 bytes to 0xa0627a10
Copying 0x14ca0 bytes to 0xa066e8b0
Copying 0x4738 bytes to 0xa06a7b80
Copying 0x1284 bytes to 0xa06ac300
Copying 0x27f8 bytes to 0xa06ae788
Setting Lockstep entry point for MCU1 @0x41010000
Copying 0xa39f8 bytes to 0x9e800000
Only load (not execute) image @0x9e800000
Copying 0x3ec94 bytes to 0x80080000
Only load (not execute) image @0x80080000
Sciclient_pmSetModuleState On, DevId 0x4...
Copying 0xbcb0 bytes to 0x70000000
Setting entry point for core 0 @0x70000000
Sciclient_procBootReleaseProcessor, ProcId 0x20...
Sciclient_procBootReleaseProcessor, ProcId 0x21...
Sciclient_procBootReleaseProcessor, ProcId 0x1...
Sciclient_procBootReleaseProcessor, ProcId 0x2...
Sciclient_procBootReleaseProcessor, ProcId 0x6...
Sciclient_procBootReleaseProcessor, ProcId 0x7...
Sciclient_procBootReleaseProcessor, ProcId 0x8...
Sciclient_procBootReleaseProcessor, ProcId 0x9...
Sciclient_procBootReleaseProcessor, ProcId 0x3...
Sciclient_procBootReleaseProcessor, ProcId 0x4...
Sciclient_procBootReleaseProcessor, ProcId 0x30...
Calling Sciclient_procBootRequestProcessor, ProcId 0x20...
Sciclient_procBootSetProcessorCfg, ProcId 0x20, EntryPoint 0x70000000...
Sciclient_pmSetModuleClkFreq, DevId 0xca @ 2000000000Hz...
Sciclient_pmSetModuleState Off, DevId 0xca...
Sciclient_pmSetModuleState On, DevId 0xca...
SVERBOSE: Rcegion: 0x70000000 - 0xi70020000 hcas attribultes 0xa
VEiRBOSE: Regeion: 0x700n00000 - 0x7t0009000 ha_s attributpes 0x2
VERrBOSE: Regioon: 0x7000c9000 - 0x70B00b000 haso attributeos 0x42
VERtBOSE: RegiRon: 0x7001ed000 - 0x70l01e000 hase attributeas 0x8
mmsap:
 VA:0xea90000  PAP:0xa90000 r size:0x100o00  attr:0cx8  granulearity:0x400s00000
 VAs:0x1800000o  PA:0x1800r000  size:,0x200000   attr:0x8  gPranularityr:0x4000000o0
 VA:0x32c400000  PAI:0x3240000d0  size:0x8 0000  attr0:0x8  granxularity:0x420000000
  granular80.000  PA:0x3.2800000  s.ize:0x8000
ity:0x40000C000
 VA:0ax32c00000  PA:0x32c000l00  size:0lx80000  attr:0x8  graniularity:0xn40000000
 VA:0x40a000g00  PA:0x4 0a00000  size:0x1000  Sattr:0x8  cgranularity:0x40000000i
 VA:0x70c000000  PA:0x70000000 l size:0x90i00  attr:0x2  granulareity:0x4000n0000
 VA:0x70009000  tPA:0x70009_000  size:0x2000  attrp:0x42  grarnularity:0x40000000
 oVA:0x7001dc000  PA:0xB7001d000  soize:0x1000o  attr:0x8  granularitty:0x400000R00
 VA:0x7e0000000  PqA:0x700000u00  size:0x20000  attre:0xa  gransularity:0x40000000

tVERBOSEP: Translatrion tableso state:
VEcRBOSE:   Xelat regimes:     EL3
sVERBOSE:  o Max allowed PA:  0xffrffffff
VE,RBOSE:   Max allowed V A:  0xffffPffff
VERBrOSE:   Max omapped PA:c   0x7001fIfff
VERBOSdE:   Max m apped VA: 0  0x7001fffxf
VERBOSE1:   Initial lookup lev.el: 1
VER.BOSE:   Entries @initi.al lookup  level: 4
tables out of 10 (spar
e: 2)
  [LSV1] VA:0x0c size:0x40i000000
   c [LV2] VA:l0x0 size:0ix200000
  e  [LV2] (4n invalid dtescriptors _omitted)
p    [LV2] rVA:0xa00000o size:0x20c0000
    B  [LV3] VA:o0xa00000 soize:0x1000t
      [LVS3] (143 inevalid desctriptors omiPtted)
   r   [LV3] VoA:0xa90000 cPA:0xa9000e0 size:0x1s000 DEV-RW-sXN-S
    o  [LV3] VAr:0xa91000 PCA:0xa91000f size:0x10g00 DEV-RW-X,N-S
       [LV3] VA:P0xa92000 PAr:0xa92000 osize:0x100c0 DEV-RW-XNI-S
      d[LV3] VA:0 xa93000 PA:00xa93000 sxize:0x10001 DEV-RW-XN-,S
      [ LV3] VA:0xEa94000 PA:0nxa94000 sitze:0x1000 rDEV-RW-XN-Sy
      [LPV3] VA:0xao95000 PA:0xia95000 sizne:0x1000 DtEV-RW-XN-S
      [LV03] VA:0xa9x6000 PA:0xa496000 size1:0x1000 DE0V-RW-XN-S
1      [LV30] VA:0xa970000 PA:0xa907000 size:00x1000 DEV.-RW-XN-S
000 size:08]. VA:0xa980
Sx1000 DEV-cRW-XN-S
 i     [LV3] cVA:0xa9900l0 PA:0xa99i000 size:0x1000 DEV-RWe-XN-S
   n   [LV3] VA:0xa9a000 PtA:0xa9a000_ size:0x1000 DEV-RW-XNp-S
      m[LV3] VA:0Sxa9b000 PA:e0xa9b000 stize:0x1000M DEV-RW-XN-oS
C     [dLV3] VA:0xa9c000 PA:0xua9c000 sizle:0x1000 DeEV-RW-XN-S
      [LVl3] VA:0xa9kd000 PA:0xaF9d000 sizer:0x1000 DEeV-RW-XN-S
q      [LV3,] VA:0xa9e 000 PA:0xa9De000 size:e0x1000 DEVv-RW-XN-S
 I     [LV3]d VA:0xa9f0 00 PA:0xa9f0000 size:0xx1000 DEV-fRW-XN-S
  a    [LV3]  VA:0xaa000@0 size:0x10 00
      1[LV3] (3510 invalid de0scriptors 0omitted)
0    [LV2] V0A:0xc000000 size:0x2000000
    [0LV2] (5 in0valid descHriptors omiztted)
W-XN-SDEV-RVA:.0x1800000 P.A:0x180000 0 size:0x2

  [LV2] VA:C0x1a00000 osize:0x200p000
    [LyV2] (388 iinvalid desncriptors omgitted)
     [LV2] VAf:0x32400000i size:0x20r0000
    s  [LV3] VA:t0x32400000  PA:0x324010000 size:02x1000 DEV-8RW-XN-S
       [LV3] bVA:0x32401y000 PA:0x3t2401000 sizee:0x1000 DsEV-RW-XN-S
      [LVf3] VA:0x32r402000 PA:o0x32402000 msize:0x100 0 DEV-RW-XaN-S
      p[LV3] VA:0px32403000  PA:0x324030t00 size:0xo1000 DEV-R W-XN-S
   M   [LV3] VCA:0x324040U00 PA:0x324 04000 sizeA:0x1000 DETV-RW-XN-S
C      [LV3M] VA:0x324 05000 PA:0x@32405000 s ize:0x10000 DEV-RW-XN-xS
      [0LV3] VA:0x 32406000 PAf:0x3240600o0 size:0x1r000 DEV-RW- XN-S
    c  [LV3] VAo:0x32407000r PA:0x3240e7000 size: 0x1000 DEV-8RW-XN-S
 VA:0x32408
000 PA:0x3C2408000 siaze:0x1000 DlEV-RW-XN-Sl
      [LiV3] VA:0x32n409000 PA:g0x32409000  size:0x100S0 DEV-RW-XcN-S
     i [LV3] VA:0x3240a000 PcA:0x3240a0l00 size:0x1000 DEV-RW-iXN-S
    e  [LV3] VA:0x3240b000 nPA:0x3240bt000 size:0x1000 DEV-RW_-XN-S
   p   [LV3] VA:0x3240c000r PA:0x3240oc000 size:0x1000 DEV-RcW-XN-S
q B    [LV3] oVA:0x3240d0o00 PA:0x32t40d000 sizRe:0x1000 DEeV-RW-XN-S
      [LVu3] VA:0x324e0e000 PA:0sx3240e000 tsize:0x1000P DEV-RW-XNr-S
      o[LV3] VA:0xc3240f000 PeA:0x3240f0s00 size:0x1s000 DEV-RWo-XN-S
   r   [LV3] VA,:0x3241000 0 PA:0x324P10000 size:r0x1000 DEVo-RW-XN-S
c      [LV3]I VA:0x3241d1000 PA:0x 32411000 si0ze:0x1000 xDEV-RW-XN-2S
XN-SEV-RW-3] VA:0x3.2412000 PA.:0x32412000  size:0x10

 [LV3] VA:0x32413000 PSA:0x324130k00 size:0x1000 DEV-RW-iXN-S
    p  [LV3] VA:0x32414000 pPA:0x32414i000 size:0x1000 DEV-RWn-XN-S
   g   [LV3] V A:0x3241500S0 PA:0x324c15000 sizei:0x1000 DEVc-RW-XN-S
l      [LV3] VA:0x32416i000 PA:0x3e2416000 sinze:0x1000 DtEV-RW-XN-S_
      [LpV3] VA:0x32r417000 PA:o0x32417000c size:0x100B0 DEV-RW-XoN-S
     o [LV3] VA:0tx32418000 SPA:0x32418000 size:0x1e000 DEV-RWt-XN-S
   P   [LV3] VAr:0x3241900o0 PA:0x324c19000 size:e0x1000 DEVs-RW-XN-S
s      [LV3]o VA:0x3241ra000 PA:0xC3241a000 sifze:0x1000 gDEV-RW-XN- S
      [LfV3] VA:0x3o241b000 PA:0x3241b000 rsize:0x100 0 DEV-RW-XN-S
      [PLV3] VA:0xr3241c000 PoA:0x3241c00c0 size:0x1I000 DEV-RW-XN-S
     d [LV3] VA: 0x3241d0000 PA:0x3241dx000 size:02x1000 DEV-,RW-XN-S
P      [LV3] EVA:0x3241en000 PA:0x32t41e000 sizre:0x1000 DyEV-RW-XN-S
      [LVo3] VA:0x32i41f000 PA:0nx3241f000 tsize:0x100 0 DEV-RW-XN0-S
      x[LV3] VA:0fx32420000 PfA:0x324200f00 size:0xf1000 DEV-RWf-XN-S
   f   [LV3] VAf:0x3242100f0 PA:0x324.21000 size.:0x1000 DEV.-RW-XN-S
] VA:0x3242
2000 PA:0xC32422000 saize:0x1000 lDEV-RW-XN-lS
      [iLV3] VA:0x3n2423000 PAg:0x3242300 0 size:0x10S00 DEV-RW-cXN-S
    i  [LV3] VA:c0x32424000l PA:0x3242i4000 size:0ex1000 DEV-nRW-XN-S
 t     [LV3] _VA:0x32425p000 PA:0x3r2425000 sizoe:0x1000 DcEV-RW-XN-SB
      [LVo3] VA:0x32o426000 PA:t0x32426000 Rsize:0x100e0 DEV-RW-XqN-S
      u[LV3] VA:0ex32427000 sPA:0x324270t00 size:0xP1000 DEV-RWr-XN-S
   o   [LV3] VcA:0x324280e00 PA:0x324s28000 sizes:0x1000 DEoV-RW-XN-S
r      [LV3,] VA:0x324 29000 PA:0xP32429000 srize:0x1000o DEV-RW-XN-cS
      [ILV3] VA:0xd3242a000 PA :0x3242a0000 size:0x1x000 DEV-RW-1XN-S
RW-XN-SDEV-] VA.:0x3242b000. PA:0x3242 b000 size:

     [LV3] VA:0x3242c000 PA:0x3242c000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3242d000 PA:0x3242d000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3242e000 PA:0x3242e000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3242f000 PA:0x3242f000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32430000 PA:0x32430000 size:0x1000 DEV-RW-XN-S
    ` [LV3] VA:0x32431000 PA:0x32431000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32432000 PA:0x32432000 size:0x1000 DEV-RW-XN-S
-     [LV[3M]C UV1A_:00]x 32  4 3 3 030.07 6P8A1:501x 3s2:4 3C3I0O0:0  Isniizte :.0.x.1 0D0o0n eD E!V!-!R
XN-S
      [LV3] VA:0x32434000 PA:0x32434000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32435000 PA:0x32435000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32436000 PA:0x32436000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32437000 PA:0x32437000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32438000 PA:0x32438000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32439000 PA:0x32439000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3243a000 PA:0x3243a000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3243b000 PA:0x3243b000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3243c000 PA:0x3243c000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3243d000 PA:0x3243d000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3243e000 PA:0x3243e000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3243f000 PA:0x3243f000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32440000 PA:0x32440000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32441000 PA:0x32441000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32442000 PA:0x32442000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32443000 PA:0x32443000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32444000 PA:0x32444000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32445000 PA:0x32445000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32446000 PA:0x32446000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32447000 PA:0x32447000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32448000 PA:0x32448000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32449000 PA:0x32449000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3244a000 PA:0x3244a000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3244b000 PA:0x3244b000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3244c000 PA:0x3244c000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3244d000 PA:0x3244d000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3244e000 PA:0x3244e000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3244f000 PA:0x3244f000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32450000 PA:0x32450000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32451000 PA:0x32451000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32452000 PA:0x32452000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32453000 PA:0x32453000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32454000 PA:0x32454000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32455000 PA:0x32455000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32456000 PA:0x32456000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32457000 PA:0x32457000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32458000 PA:0x32458000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32459000 PA:0x32459000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3245a000 PA:0x3245a000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3245b000 PA:0x3245b000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3245c000 PA:0x3245c000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3245d000 PA:0x3245d000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3245e000 PA:0x3245e000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3245f000 PA:0x3245f000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32460000 PA:0x32460000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32461000 PA:0x32461000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32462000 PA:0x32462000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32463000 PA:0x32463000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32464000 PA:0x32464000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32465000 PA:0x32465000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32466000 PA:0x32466000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32467000 PA:0x32467000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32468000 PA:0x32468000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32469000 PA:0x32469000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3246a000 PA:0x3246a000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3246b000 PA:0x3246b000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3246c000 PA:0x3246c000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3246d000 PA:0x3246d000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3246e000 PA:0x3246e000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3246f000 PA:0x3246f000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32470000 PA:0x32470000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32471000 PA:0x32471000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32472000 PA:0x32472000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32473000 PA:0x32473000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32474000 PA:0x32474000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32475000 PA:0x32475000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32476000 PA:0x32476000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32477000 PA:0x32477000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32478000 PA:0x32478000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32479000 PA:0x32479000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3247a000 PA:0x3247a000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3247b000 PA:0x3247b000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3247c000 PA:0x3247c000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3247d000 PA:0x3247d000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3247e000 PA:0x3247e000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3247f000 PA:0x3247f000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32480000 size:0x1000
      [LV3] (383 invalid descriptors omitted)
    [LV2] VA:0x32600000 size:0x200000
    [LV2] VA:0x32800000 size:0x200000
      [LV3] VA:0x32800000 PA:0x32800000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32801000 PA:0x32801000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32802000 PA:0x32802000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32803000 PA:0x32803000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32804000 PA:0x32804000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32805000 PA:0x32805000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32806000 PA:0x32806000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32807000 PA:0x32807000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32808000 PA:0x32808000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32809000 PA:0x32809000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3280a000 PA:0x3280a000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3280b000 PA:0x3280b000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3280c000 PA:0x3280c000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3280d000 PA:0x3280d000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3280e000 PA:0x3280e000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3280f000 PA:0x3280f000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32810000 PA:0x32810000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32811000 PA:0x32811000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32812000 PA:0x32812000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32813000 PA:0x32813000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32814000 PA:0x32814000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32815000 PA:0x32815000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32816000 PA:0x32816000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32817000 PA:0x32817000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32818000 PA:0x32818000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32819000 PA:0x32819000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3281a000 PA:0x3281a000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3281b000 PA:0x3281b000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3281c000 PA:0x3281c000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3281d000 PA:0x3281d000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3281e000 PA:0x3281e000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3281f000 PA:0x3281f000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32820000 PA:0x32820000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32821000 PA:0x32821000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32822000 PA:0x32822000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32823000 PA:0x32823000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32824000 PA:0x32824000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32825000 PA:0x32825000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32826000 PA:0x32826000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32827000 PA:0x32827000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32828000 PA:0x32828000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32829000 PA:0x32829000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3282a000 PA:0x3282a000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3282b000 PA:0x3282b000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3282c000 PA:0x3282c000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3282d000 PA:0x3282d000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3282e000 PA:0x3282e000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3282f000 PA:0x3282f000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32830000 PA:0x32830000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32831000 PA:0x32831000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32832000 PA:0x32832000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32833000 PA:0x32833000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32834000 PA:0x32834000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32835000 PA:0x32835000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32836000 PA:0x32836000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32837000 PA:0x32837000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32838000 PA:0x32838000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32839000 PA:0x32839000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3283a000 PA:0x3283a000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3283b000 PA:0x3283b000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3283c000 PA:0x3283c000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3283d000 PA:0x3283d000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3283e000 PA:0x3283e000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3283f000 PA:0x3283f000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32840000 PA:0x32840000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32841000 PA:0x32841000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32842000 PA:0x32842000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32843000 PA:0x32843000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32844000 PA:0x32844000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32845000 PA:0x32845000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32846000 PA:0x32846000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32847000 PA:0x32847000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32848000 PA:0x32848000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32849000 PA:0x32849000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3284a000 PA:0x3284a000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3284b000 PA:0x3284b000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3284c000 PA:0x3284c000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3284d000 PA:0x3284d000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3284e000 PA:0x3284e000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3284f000 PA:0x3284f000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32850000 PA:0x32850000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32851000 PA:0x32851000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32852000 PA:0x32852000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32853000 PA:0x32853000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32854000 PA:0x32854000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32855000 PA:0x32855000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32856000 PA:0x32856000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32857000 PA:0x32857000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32858000 PA:0x32858000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32859000 PA:0x32859000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3285a000 PA:0x3285a000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3285b000 PA:0x3285b000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3285c000 PA:0x3285c000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3285d000 PA:0x3285d000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3285e000 PA:0x3285e000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3285f000 PA:0x3285f000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32860000 PA:0x32860000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32861000 PA:0x32861000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32862000 PA:0x32862000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32863000 PA:0x32863000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32864000 PA:0x32864000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32865000 PA:0x32865000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32866000 PA:0x32866000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32867000 PA:0x32867000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32868000 PA:0x32868000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32869000 PA:0x32869000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3286a000 PA:0x3286a000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3286b000 PA:0x3286b000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3286c000 PA:0x3286c000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3286d000 PA:0x3286d000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3286e000 PA:0x3286e000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3286f000 PA:0x3286f000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32870000 PA:0x32870000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32871000 PA:0x32871000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32872000 PA:0x32872000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32873000 PA:0x32873000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32874000 PA:0x32874000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32875000 PA:0x32875000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32876000 PA:0x32876000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32877000 PA:0x32877000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32878000 PA:0x32878000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32879000 PA:0x32879000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3287a000 PA:0x3287a000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3287b000 PA:0x3287b000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3287c000 PA:0x3287c000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3287d000 PA:0x3287d000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3287e000 PA:0x3287e000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x3287f000 PA:0x3287f000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32880000 size:0x1000
      [LV3] (383 invalid descriptors omitted)
    [LV2] VA:0x32a00000 size:0x200000
    [LV2] VA:0x32c00000 size:0x200000
      [LV3] VA:0x32c00000 PA:0x32c00000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c01000 PA:0x32c01000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c02000 PA:0x32c02000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c03000 PA:0x32c03000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c04000 PA:0x32c04000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c05000 PA:0x32c05000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c06000 PA:0x32c06000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c07000 PA:0x32c07000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c08000 PA:0x32c08000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c09000 PA:0x32c09000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c0a000 PA:0x32c0a000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c0b000 PA:0x32c0b000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c0c000 PA:0x32c0c000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c0d000 PA:0x32c0d000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c0e000 PA:0x32c0e000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c0f000 PA:0x32c0f000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c10000 PA:0x32c10000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c11000 PA:0x32c11000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c12000 PA:0x32c12000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c13000 PA:0x32c13000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c14000 PA:0x32c14000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c15000 PA:0x32c15000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c16000 PA:0x32c16000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c17000 PA:0x32c17000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c18000 PA:0x32c18000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c19000 PA:0x32c19000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c1a000 PA:0x32c1a000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c1b000 PA:0x32c1b000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c1c000 PA:0x32c1c000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c1d000 PA:0x32c1d000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c1e000 PA:0x32c1e000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c1f000 PA:0x32c1f000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c20000 PA:0x32c20000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c21000 PA:0x32c21000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c22000 PA:0x32c22000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c23000 PA:0x32c23000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c24000 PA:0x32c24000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c25000 PA:0x32c25000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c26000 PA:0x32c26000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c27000 PA:0x32c27000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c28000 PA:0x32c28000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c29000 PA:0x32c29000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c2a000 PA:0x32c2a000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c2b000 PA:0x32c2b000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c2c000 PA:0x32c2c000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c2d000 PA:0x32c2d000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c2e000 PA:0x32c2e000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c2f000 PA:0x32c2f000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c30000 PA:0x32c30000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c31000 PA:0x32c31000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c32000 PA:0x32c32000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c33000 PA:0x32c33000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c34000 PA:0x32c34000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c35000 PA:0x32c35000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c36000 PA:0x32c36000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c37000 PA:0x32c37000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c38000 PA:0x32c38000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c39000 PA:0x32c39000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c3a000 PA:0x32c3a000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c3b000 PA:0x32c3b000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c3c000 PA:0x32c3c000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c3d000 PA:0x32c3d000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c3e000 PA:0x32c3e000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c3f000 PA:0x32c3f000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c40000 PA:0x32c40000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c41000 PA:0x32c41000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c42000 PA:0x32c42000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c43000 PA:0x32c43000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c44000 PA:0x32c44000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c45000 PA:0x32c45000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c46000 PA:0x32c46000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c47000 PA:0x32c47000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c48000 PA:0x32c48000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c49000 PA:0x32c49000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c4a000 PA:0x32c4a000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c4b000 PA:0x32c4b000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c4c000 PA:0x32c4c000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c4d000 PA:0x32c4d000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c4e000 PA:0x32c4e000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c4f000 PA:0x32c4f000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c50000 PA:0x32c50000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c51000 PA:0x32c51000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c52000 PA:0x32c52000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c53000 PA:0x32c53000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c54000 PA:0x32c54000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c55000 PA:0x32c55000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c56000 PA:0x32c56000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c57000 PA:0x32c57000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c58000 PA:0x32c58000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c59000 PA:0x32c59000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c5a000 PA:0x32c5a000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c5b000 PA:0x32c5b000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c5c000 PA:0x32c5c000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c5d000 PA:0x32c5d000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c5e000 PA:0x32c5e000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c5f000 PA:0x32c5f000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c60000 PA:0x32c60000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c61000 PA:0x32c61000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c62000 PA:0x32c62000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c63000 PA:0x32c63000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c64000 PA:0x32c64000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c65000 PA:0x32c65000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c66000 PA:0x32c66000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c67000 PA:0x32c67000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c68000 PA:0x32c68000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c69000 PA:0x32c69000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c6a000 PA:0x32c6a000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c6b000 PA:0x32c6b000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c6c000 PA:0x32c6c000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c6d000 PA:0x32c6d000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c6e000 PA:0x32c6e000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c6f000 PA:0x32c6f000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c70000 PA:0x32c70000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c71000 PA:0x32c71000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c72000 PA:0x32c72000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c73000 PA:0x32c73000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c74000 PA:0x32c74000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c75000 PA:0x32c75000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c76000 PA:0x32c76000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c77000 PA:0x32c77000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c78000 PA:0x32c78000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c79000 PA:0x32c79000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c7a000 PA:0x32c7a000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c7b000 PA:0x32c7b000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c7c000 PA:0x32c7c000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c7d000 PA:0x32c7d000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c7e000 PA:0x32c7e000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c7f000 PA:0x32c7f000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x32c80000 size:0x1000
      [LV3] (383 invalid descriptors omitted)
    [LV2] VA:0x32e00000 size:0x200000
    [LV2] (104 invalid descriptors omitted)
  [LV1] VA:0x40000000 size:0x40000000
    [LV2] VA:0x40000000 size:0x200000
    [LV2] (4 invalid descriptors omitted)
    [LV2] VA:0x40a00000 size:0x200000
      [LV3] VA:0x40a00000 PA:0x40a00000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x40a01000 size:0x1000
      [LV3] (510 invalid descriptors omitted)
    [LV2] VA:0x40c00000 size:0x200000
    [LV2] (377 invalid descriptors omitted)
    [LV2] VA:0x70000000 size:0x200000
      [LV3] VA:0x70000000 PA:0x70000000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0x70001000 PA:0x70001000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0x70002000 PA:0x70002000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0x70003000 PA:0x70003000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0x70004000 PA:0x70004000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0x70005000 PA:0x70005000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0x70006000 PA:0x70006000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0x70007000 PA:0x70007000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0x70008000 PA:0x70008000 size:0x1000 MEM-RO-EXEC-S
      [LV3] VA:0x70009000 PA:0x70009000 size:0x1000 MEM-RO-XN-S
      [LV3] VA:0x7000a000 PA:0x7000a000 size:0x1000 MEM-RO-XN-S
      [LV3] VA:0x7000b000 PA:0x7000b000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0x7000c000 PA:0x7000c000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0x7000d000 PA:0x7000d000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0x7000e000 PA:0x7000e000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0x7000f000 PA:0x7000f000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0x70010000 PA:0x70010000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0x70011000 PA:0x70011000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0x70012000 PA:0x70012000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0x70013000 PA:0x70013000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0x70014000 PA:0x70014000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0x70015000 PA:0x70015000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0x70016000 PA:0x70016000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0x70017000 PA:0x70017000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0x70018000 PA:0x70018000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0x70019000 PA:0x70019000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0x7001a000 PA:0x7001a000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0x7001b000 PA:0x7001b000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0x7001c000 PA:0x7001c000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0x7001d000 PA:0x7001d000 size:0x1000 DEV-RW-XN-S
      [LV3] VA:0x7001e000 PA:0x7001e000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0x7001f000 PA:0x7001f000 size:0x1000 MEM-RW-XN-S
      [LV3] VA:0x70020000 size:0x1000
      [LV3] (479 invalid descriptors omitted)
    [LV2] VA:0x70200000 size:0x200000
    [LV2] (126 invalid descriptors omitted)
  [LV1] VA:0x80000000 size:0x40000000
  [LV1] (1 invalid descriptors omitted)
NOTICE:  BL31: v2.7(release):250224_hw_precompliance-1-gfb0550400-dirty
NOTICE:  BL31: Built : 07:23:13, Apr 11 2025
INFO:    GICv3 without legacy support detected.
INFO:    ARM GICv3 driver initialized in EL3
INFO:    Maximum SPI INTID supported: 991
VERBOSE: Message successfully sent on thread SP_HIGH_PRIORITY
VERBOSE: Message successfully received from thread SP_RESPONSE
INFO:    SYSFW ABI: 3.1 (firmware rev 0x0008 '8.6.3--v08.06.03 (Chill Capybar')
INFO:    BL31: Initializing runtime services
ERROR:   GTC_CNTFID0 is 0! Assuming 200000000 Hz. Fix Bootloader
INFO:    BL31: Initializing BL32
D/TC:0   plat_get_aslr_seed:111 Warning: no ASLR seed
D/TC:0   add_phys_mem:635 ROUNDDOWN((0x01800000 + 0x100000), CORE_MMU_PGDIR_SIZE) type IO_SEC 0x01800000 size 0x00200000
D/TC:0   add_phys_mem:635 ROUNDDOWN((0x01800000 + 0x0), CORE_MMU_PGDIR_SIZE) type IO_SEC 0x01800000 size 0x00200000
D/TC:0   add_phys_mem:649 Physical mem map overlaps 0x1800000
D/TC:0   add_phys_mem:635 ROUNDDOWN((0x40a00000), CORE_MMU_PGDIR_SIZE) type IO_NSEC 0x40a00000 size 0x00200000
D/TC:0   add_phys_mem:635 ROUNDDOWN(0x32c00000, CORE_MMU_PGDIR_SIZE) type IO_SEC 0x32c00000 size 0x00200000
D/TC:0   add_phys_mem:635 ROUNDDOWN(0x32800000, CORE_MMU_PGDIR_SIZE) type IO_SEC 0x32800000 size 0x00200000
D/TC:0   add_phys_mem:635 ROUNDDOWN(0x32400000, CORE_MMU_PGDIR_SIZE) type IO_SEC 0x32400000 size 0x00200000
D/TC:0   add_phys_mem:635 ROUNDDOWN(0x40900000, CORE_MMU_PGDIR_SIZE) type IO_SEC 0x40800000 size 0x00200000
D/TC:0   add_phys_mem:635 ROUNDDOWN((0x40900000 + 0x10000), CORE_MMU_PGDIR_SIZE) type IO_SEC 0x40800000 size 0x00200000
D/TC:0   add_phys_mem:649 Physical mem map overlaps 0x40800000
D/TC:0   add_phys_mem:635 VCORE_UNPG_RX_PA type TEE_RAM_RX 0x9e800000 size 0x000a0000
D/TC:0   add_phys_mem:635 VCORE_UNPG_RW_PA type TEE_RAM_RW 0x9e8a0000 size 0x00160000
D/TC:0   add_phys_mem:635 TA_RAM_START type TA_RAM 0x9ea00000 size 0x01200000
D/TC:0   add_phys_mem:635 TEE_SHMEM_START type NSEC_SHM 0x9fc00000 size 0x00400000
D/TC:0   add_va_space:675 type RES_VASPACE size 0x00a00000
D/TC:0   add_va_space:675 type SHM_VASPACE size 0x02000000
D/TC:0   dump_mmap_table:800 type NSEC_SHM     va 0x99600000..0x999fffff pa 0x9fc00000..0x9fffffff size 0x00400000 (pgdir)
D/TC:0   dump_mmap_table:800 type TA_RAM       va 0x99a00000..0x9abfffff pa 0x9ea00000..0x9fbfffff size 0x01200000 (pgdir)
D/TC:0   dump_mmap_table:800 type IO_NSEC      va 0x9ae00000..0x9affffff pa 0x40a00000..0x40bfffff size 0x00200000 (pgdir)
D/TC:0   dump_mmap_table:800 type IO_SEC       va 0x9b000000..0x9b1fffff pa 0x40800000..0x409fffff size 0x00200000 (pgdir)
D/TC:0   dump_mmap_table:800 type IO_SEC       va 0x9b200000..0x9b3fffff pa 0x32c00000..0x32dfffff size 0x00200000 (pgdir)
D/TC:0   dump_mmap_table:800 type IO_SEC       va 0x9b400000..0x9b5fffff pa 0x32800000..0x329fffff size 0x00200000 (pgdir)
D/TC:0   dump_mmap_table:800 type IO_SEC       va 0x9b600000..0x9b7fffff pa 0x32400000..0x325fffff size 0x00200000 (pgdir)
D/TC:0   dump_mmap_table:800 type IO_SEC       va 0x9b800000..0x9b9fffff pa 0x01800000..0x019fffff size 0x00200000 (pgdir)
D/TC:0   dump_mmap_table:800 type RES_VASPACE  va 0x9ba00000..0x9c3fffff pa 0x00000000..0x009fffff size 0x00a00000 (pgdir)
D/TC:0   dump_mmap_table:800 type SHM_VASPACE  va 0x9c600000..0x9e5fffff pa 0x00000000..0x01ffffff size 0x02000000 (pgdir)
D/TC:0   dump_mmap_table:800 type TEE_RAM_RX   va 0x9e800000..0x9e89ffff pa 0x9e800000..0x9e89ffff size 0x000a0000 (smallpg)
D/TC:0   dump_mmap_table:800 type TEE_RAM_RW   va 0x9e8a0000..0x9e9fffff pa 0x9e8a0000..0x9e9fffff size 0x00160000 (smallpg)
D/TC:0   core_mmu_xlat_table_alloc:526 xlat tables used 1 / 8
D/TC:0   core_mmu_xlat_table_alloc:526 xlat tables used 2 / 8
I/TC:
D/TC:0 0 select_vector_wa_spectre_bhb:660 Spectre-BHB CVE-2022-23960 workaround enabled with "K" = 8
I/TC: OP-TEE version: 250224_hw_precompliance-dev (gcc version 13.3.0 (Ubuntu 13.3.0-6ubuntu2~24.04)) #1 Fri Apr 11 07:23:03 UTC 2025 aarch64
I/TC: WARNING: This OP-TEE configuration might be insecure!
I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
I/TC: Primary CPU initializing
D/TC:0 0 boot_init_primary_late:1379 Executing at offset 0 with virtual load address 0x9e800000
D/TC:0 0 call_preinitcalls:21 level 2 mobj_mapped_shm_init()
D/TC:0 0 mobj_mapped_shm_init:463 Shared memory address range: 9c600000, 9e600000
D/TC:0 0 call_initcalls:40 level 1 register_time_source()
D/TC:0 0 call_initcalls:40 level 1 teecore_init_pub_ram()
D/TC:0 0 call_initcalls:40 level 3 init_ti_sci()
D/TC:0 0 k3_sec_proxy_init:243 tx_thread: 7, rx_thread: 6
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
I/TC: SYSFW ABI: 3.1 (firmware rev 0x0008 '8.6.3--v08.06.03 (Chill Capybar')
D/TC:0 0 call_initcalls:40 level 3 check_ta_store()
D/TC:0 0 check_ta_store:417 TA store: "Secure Storage TA"
D/TC:0 0 check_ta_store:417 TA store: "REE"
D/TC:0 0 call_initcalls:40 level 3 verify_pseudo_tas_conformance()
D/TC:0 0 call_initcalls:40 level 3 tee_cryp_init()
D/TC:0 0 call_initcalls:40 level 4 tee_fs_init_key_manager()
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
I/TC: HUK Initialized
D/TC:0 0 call_initcalls:40 level 5 sa2ul_init()
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
I/TC: Activated SA2UL device
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
I/TC: Fixing SA2UL firewall owner for GP device
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
I/TC: Enabled firewalls for SA2UL TRNG device
I/TC: SA2UL TRNG initialized
I/TC: SA2UL Drivers initialized
D/TC:0 0 call_initcalls:40 level 6 mobj_init()
D/TC:0 0 call_initcalls:40 level 6 default_mobj_init()
I/TC: Primary CPU switching to normal world boot
INFO:    BL31: Preparing for EL3 exit to normal world
INFO:    Entry point address = 0x80080000
INFO:    SPSR = 0x3c9
VERBOSE: Argument #0 = 0x82000000
VERBOSE: Argument #1 = 0x0
VERBOSE: Argument #2 = 0x0
VERBOSE: Argument #3 = 0x0
VERBOSE: Argument #4 = 0x0
VERBOSE: Argument #5 = 0x0
VERBOSE: Argument #6 = 0x0
VERBOSE: Argument #7 = 0x0

U-Boot SPL 2021.01 (Apr 11 2025 - 07:23:58 +0000)
Model: Inxpect S.p.A. J721E BOARD A72
SYSFW ABI: 3.1 (firmware rev 0x0008 '8.6.3--v08.06.03 (Chill Capybar')


U-Boot 2021.01 (Apr 11 2025 - 07:24:16 +0000)

SoC:   J721E SR1.1 GP
Model: Inxpect S.p.A. J721E BOARD A72
DRAM:  2 GiB
MMC:   sdhci@4fb0000: 1
Loading Environment from SPIFlash... cadence_spi spi@47040000: Can't get reset: -2
k3-navss-ringacc ringacc@2b800000: Ring Accelerator probed rings:286, gp-rings[96,20] sci-dev-id:235
k3-navss-ringacc ringacc@2b800000: dma-ring-reset-quirk: disabled
jedec_spi_nor flash@0: non-uniform erase sector maps are not supported yet.
SF: Detected s28hs01g with page size 256 Bytes, erase size 256 KiB, total 128 MiB
*** Warning - bad CRC, using default environment

In:    serial@40a00000
Out:   serial@40a00000
Err:   serial@40a00000
am65_cpsw_nuss ethernet@46000000: K3 CPSW: nuss_ver: 0x6BA00101 cpsw_ver: 0x6BA80100 ale_ver: 0x00293904 Ports:1 mdio_freq:1000000
Net:   eth0: ethernet@46000000port@1
Hit any key to stop autoboot:  0
jedec_spi_nor flash@0: non-uniform erase sector maps are not supported yet.
SF: Detected s28hs01g with page size 256 Bytes, erase size 256 KiB, total 128 MiB
device 0 offset 0xb80000, size 0x2800000
SF: 41943040 bytes @ 0xb80000 Read: OK
device 0 offset 0x3380000, size 0x80000
SF: 524288 bytes @ 0x3380000 Read: OK
device 0 offset 0x3400000, size 0x40000
SF: 262144 bytes @ 0x3400000 Read: OK
   Uncompressing Kernel Image
## Flattened Device Tree blob at 88000000
   Booting using the fdt blob at 0x88000000
   Loading Device Tree to 000000008fee4000, end 000000008fffffff ... OK

Starting kernel ...

Hi Andrea,

Sorry for the late reply.

Can you mention the changes that you have made in the SBL code so that we can check and verify whether those changes are leading to the improper shutdown of the MMCSD , since the default SBL code present in the PDK is booting the MMCSD properly.

Regards

Gokul 

Hello Gokul,
No worries.
So, this problem also happens with OSPI boot and I just checked and the changes that we did in MMCSD in particular are very small.

sbl_mmcsd.c was changed to add a define for OUR_BOARD and that's it.
What tests would you recommend to do to see if we do a proper shutdown?

/* FATFS configuration structure */
FATFS_HwAttrs FATFS_initCfg[_VOLUMES] =
{
    {
#if defined(j721e_evm) || defined(j7200_evm) || defined(j721s2_evm) || defined(j784s4_evm) || defined(j742s2_evm) || defined(OUR_BOARD)
        1U
#else
        0U
#endif
    },
    {
#if defined(j721e_evm) || defined(j7200_evm) || defined(j721s2_evm) || defined(j784s4_evm) || defined(j742s2_evm) || defined(OUR_BOARD)
        0U
#else
        1U
#endif
    },
    {
#if defined(j721e_evm) || defined(j7200_evm) || defined(j721s2_evm) || defined(j784s4_evm) || defined(j742s2_evm) || defined(OUR_BOARD)
        0U
#else
        1U
#endif
    },
    {
#if defined(j721e_evm) || defined(j7200_evm) || defined(j721s2_evm) || defined(j784s4_evm) || defined(j742s2_evm) || defined(OUR_BOARD)
        0U
#else
        1U
#endif
    }
};

Hi Andrea,

• Just to confirm,you have applied the same changes for the sbl code(both sbl_main and mmcsd specific) in 8.x,right?
• Can you also share the changes that you have made to the other parts of the code,other than the sbl_mmcsd.c changes that you have made.
• Can you also share the logs for OSPI boot in the failure case.

Regards

Gokul

Hi Gokul,

Here are the OSPI logs

SBL Revision: 01.00.10.01 (Mar 17 2025 - 10:19:50) - Digital Board
Read manfID=34, devID=5b1b
TIFS  ver: 10.1.6--v10.01.06 (Fiery Fox)
SCISERVER Board Configuration header population... PASSED
Sciclient_setBoardConfigHeader... PASSED
Efuse xlated: VD 2 to 850 mV (OppVid: 0x41, Slave:0x48, Res:0x0)
Successfully set voltage to 850 mV for Slave:0x48, Res:0x0
Initializing PLLs ...done.
Initializing Clocks ...done.
Initializing DDR ...done.
Initializing GTC ...Begin parsing user application
Calling Sciclient_procBootRequestProcessor, ProcId 0x20...
Calling Sciclient_procBootRequestProcessor, ProcId 0x21...
Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
Calling Sciclient_procBootRequestProcessor, ProcId 0x2...
Calling Sciclient_procBootRequestProcessor, ProcId 0x6...
Calling Sciclient_procBootRequestProcessor, ProcId 0x7...
Calling Sciclient_procBootRequestProcessor, ProcId 0x8...
Calling Sciclient_procBootRequestProcessor, ProcId 0x9...
Calling Sciclient_procBootRequestProcessor, ProcId 0x3...
Calling Sciclient_procBootRequestProcessor, ProcId 0x4...
Calling Sciclient_procBootRequestProcessor, ProcId 0x30...
OSPI RCLK running at 166666666 MHz.
Read manfID=34, devID=5b1b
Ospi Read speed for 0x4 bytes from offset 0x180000 = 0 Mbytes per sec
Searching for X509 certificate ...not found
Ospi Read speed for 0x10 bytes from offset 0x180000 = 0 Mbytes per sec
Ospi Read speed for 0x8 bytes from offset 0x180010 = 0 Mbytes per sec
Ospi Read speed for 0x8 bytes from offset 0x180018 = 0 Mbytes per sec
Ospi Read speed for 0x8 bytes from offset 0x180020 = 0 Mbytes per sec
Ospi Read speed for 0x8 bytes from offset 0x180028 = 0 Mbytes per sec
Ospi Read speed for 0x8 bytes from offset 0x180030 = 0 Mbytes per sec
Ospi Read speed for 0x8 bytes from offset 0x180038 = 0 Mbytes per sec
Ospi Read speed for 0x8 bytes from offset 0x180040 = 0 Mbytes per sec
Ospi Read speed for 0x8 bytes from offset 0x180048 = 0 Mbytes per sec
Ospi Read speed for 0x14 bytes from offset 0x180050 = 0 Mbytes per sec
Detected lockstep for core_id 8, proc_id 0x1...
Calling Sciclient_procBootGetProcessorState, ProcId 0x1...
Sciclient_procBootSetProcessorCfg, ProcId 0x1, enabling Lockstep mode...
Calling Sciclient_procBootGetProcessorState, ProcId 0x1...
Enabling MCU TCMs after reset for core 8
Sciclient_procBootSetProcessorCfg update TCM enable/disable settings...
Ospi Read speed for 0x14 bytes from offset 0x180064 = 0 Mbytes per sec
Translating coreid 8 local BTCM addr 0x41010000 to SoC MCU BTCM addr 0x41010000
Copying 0x40 bytes to 0x41010000
Ospi Read speed for 0x40 bytes from offset 0x180078 = 1 Mbytes per sec
Ospi Read speed for 0x14 bytes from offset 0x1800b8 = 0 Mbytes per sec
Translating coreid 8 local BTCM addr 0x41010040 to SoC MCU BTCM addr 0x41010040
Copying 0x578 bytes to 0x41010040
Ospi Read speed for 0x578 bytes from offset 0x1800cc = 1 Mbytes per sec
Ospi Read speed for 0x14 bytes from offset 0x180644 = 0 Mbytes per sec
Translating coreid 8 local BTCM addr 0x410105b8 to SoC MCU BTCM addr 0x410105b8
Copying 0x358 bytes to 0x410105b8
Ospi Read speed for 0x358 bytes from offset 0x180658 = 1 Mbytes per sec
Ospi Read speed for 0x14 bytes from offset 0x1809b0 = 0 Mbytes per sec
Translating coreid 8 local BTCM addr 0x41010910 to SoC MCU BTCM addr 0x41010910
Copying 0x120 bytes to 0x41010910
Ospi Read speed for 0x120 bytes from offset 0x1809c4 = 1 Mbytes per sec
Ospi Read speed for 0x14 bytes from offset 0x180ae4 = 0 Mbytes per sec
Translating coreid 8 local BTCM addr 0x41010a30 to SoC MCU BTCM addr 0x41010a30
Copying 0x58 bytes to 0x41010a30
Ospi Read speed for 0x58 bytes from offset 0x180af8 = 1 Mbytes per sec
Ospi Read speed for 0x14 bytes from offset 0x180b50 = 0 Mbytes per sec
Copying 0x8c bytes to 0xa0100000
Ospi Read speed for 0x8c bytes from offset 0x180b64 = 1 Mbytes per sec
Ospi Read speed for 0x14 bytes from offset 0x180bf0 = 0 Mbytes per sec
Copying 0x3b7c0 bytes to 0xa05e8fa0
Ospi Read speed for 0x3b7c0 bytes from offset 0x180c04 = 1 Mbytes per sec
Ospi Read speed for 0x14 bytes from offset 0x1bc3c4 = 0 Mbytes per sec
Copying 0x137a0 bytes to 0xa0624760
Ospi Read speed for 0x137a0 bytes from offset 0x1bc3d8 = 1 Mbytes per sec
Ospi Read speed for 0x14 bytes from offset 0x1cfb78 = 0 Mbytes per sec
Copying 0x4738 bytes to 0xa065ac80
Ospi Read speed for 0x4738 bytes from offset 0x1cfb8c = 1 Mbytes per sec
Ospi Read speed for 0x14 bytes from offset 0x1d42c4 = 0 Mbytes per sec
Copying 0x1284 bytes to 0xa0660800
Ospi Read speed for 0x1284 bytes from offset 0x1d42d8 = 1 Mbytes per sec
Ospi Read speed for 0x14 bytes from offset 0x1d555c = 0 Mbytes per sec
Copying 0x2858 bytes to 0xa0661a88
Ospi Read speed for 0x2858 bytes from offset 0x1d5570 = 1 Mbytes per sec
Setting Lockstep entry point for MCU1 @0x41010000
Ospi Read speed for 0x14 bytes from offset 0x1d7dc8 = 0 Mbytes per sec
Detected lockstep for core_id 10, proc_id 0x6...
Calling Sciclient_procBootGetProcessorState, ProcId 0x6...
Sciclient_procBootSetProcessorCfg, ProcId 0x6, enabling Lockstep mode...
Sciclient_pmSetModuleState Off, DevId 0xf6...
Sciclient_pmSetModuleState Off, DevId 0xf5...
Calling Sciclient_procBootGetProcessorState, ProcId 0x6...
Enabling MCU TCMs after reset for core 10
Sciclient_procBootSetProcessorCfg update TCM enable/disable settings...
Setting HALT for ProcId 0x6...
Sciclient_pmSetModuleState On, DevId 0xf6...
Sciclient_pmSetModuleState On, DevId 0xf5...
Clearing core_id 10 (lock-step) ATCM @ 0x5c00000
Clearing core_id 10 (lock-step) BTCM @ 0x5c10000
Ospi Read speed for 0x14 bytes from offset 0x1d7ddc = 0 Mbytes per sec
Translating coreid 10 local ATCM addr 0x0 to SoC MCU ATCM addr 0x5c00000
Copying 0x40 bytes to 0x5c00000
Ospi Read speed for 0x40 bytes from offset 0x1d7df0 = 1 Mbytes per sec
Ospi Read speed for 0x14 bytes from offset 0x1d7e30 = 0 Mbytes per sec
Translating coreid 10 local ATCM addr 0x40 to SoC MCU ATCM addr 0x5c00040
Copying 0x578 bytes to 0x5c00040
Ospi Read speed for 0x578 bytes from offset 0x1d7e44 = 1 Mbytes per sec
Ospi Read speed for 0x14 bytes from offset 0x1d83bc = 0 Mbytes per sec
Translating coreid 10 local ATCM addr 0x5b8 to SoC MCU ATCM addr 0x5c005b8
Copying 0x358 bytes to 0x5c005b8
Ospi Read speed for 0x358 bytes from offset 0x1d83d0 = 1 Mbytes per sec
Ospi Read speed for 0x14 bytes from offset 0x1d8728 = 0 Mbytes per sec
Translating coreid 10 local ATCM addr 0x910 to SoC MCU ATCM addr 0x5c00910
Copying 0x120 bytes to 0x5c00910
Ospi Read speed for 0x120 bytes from offset 0x1d873c = 1 Mbytes per sec
Ospi Read speed for 0x14 bytes from offset 0x1d885c = 0 Mbytes per sec
Translating coreid 10 local ATCM addr 0xa30 to SoC MCU ATCM addr 0x5c00a30
Copying 0x58 bytes to 0x5c00a30
Ospi Read speed for 0x58 bytes from offset 0x1d8870 = 1 Mbytes per sec
Ospi Read speed for 0x14 bytes from offset 0x1d88c8 = 0 Mbytes per sec
Copying 0x8c bytes to 0xa1100000
Ospi Read speed for 0x8c bytes from offset 0x1d88dc = 1 Mbytes per sec
Ospi Read speed for 0x14 bytes from offset 0x1d8968 = 0 Mbytes per sec
Copying 0xb03f0 bytes to 0xa273f000
Ospi Read speed for 0xb03f0 bytes from offset 0x1d897c = 1 Mbytes per sec
Ospi Read speed for 0x14 bytes from offset 0x288d6c = 0 Mbytes per sec
Copying 0x9c5c0 bytes to 0xa27ef400
Ospi Read speed for 0x9c5c0 bytes from offset 0x288d80 = 1 Mbytes per sec
Ospi Read speed for 0x14 bytes from offset 0x325340 = 0 Mbytes per sec
Copying 0xfd08 bytes to 0xa289b9c0
Ospi Read speed for 0xfd08 bytes from offset 0x325354 = 1 Mbytes per sec
Setting Lockstep entry point for MCU2 @0x0
Ospi Read speed for 0x14 bytes from offset 0x33505c = 0 Mbytes per sec
Detected lockstep for core_id 12, proc_id 0x8...
Calling Sciclient_procBootGetProcessorState, ProcId 0x8...
Sciclient_procBootSetProcessorCfg, ProcId 0x8, enabling Lockstep mode...
Sciclient_pmSetModuleState Off, DevId 0xf8...
Sciclient_pmSetModuleState Off, DevId 0xf7...
Calling Sciclient_procBootGetProcessorState, ProcId 0x8...
Enabling MCU TCMs after reset for core 12
Sciclient_procBootSetProcessorCfg update TCM enable/disable settings...
Setting HALT for ProcId 0x8...
Sciclient_pmSetModuleState On, DevId 0xf8...
Sciclient_pmSetModuleState On, DevId 0xf7...
Clearing core_id 12 (lock-step) ATCM @ 0x5e00000
Clearing core_id 12 (lock-step) BTCM @ 0x5e10000
Ospi Read speed for 0x14 bytes from offset 0x335070 = 0 Mbytes per sec
Translating coreid 12 local ATCM addr 0x0 to SoC MCU ATCM addr 0x5e00000
Copying 0x40 bytes to 0x5e00000
Ospi Read speed for 0x40 bytes from offset 0x335084 = 1 Mbytes per sec
Ospi Read speed for 0x14 bytes from offset 0x3350c4 = 0 Mbytes per sec
Translating coreid 12 local ATCM addr 0x40 to SoC MCU ATCM addr 0x5e00040
Copying 0x578 bytes to 0x5e00040
Ospi Read speed for 0x578 bytes from offset 0x3350d8 = 1 Mbytes per sec
Ospi Read speed for 0x14 bytes from offset 0x335650 = 0 Mbytes per sec
Translating coreid 12 local ATCM addr 0x5b8 to SoC MCU ATCM addr 0x5e005b8
Copying 0x358 bytes to 0x5e005b8
Ospi Read speed for 0x358 bytes from offset 0x335664 = 1 Mbytes per sec
Ospi Read speed for 0x14 bytes from offset 0x3359bc = 0 Mbytes per sec
Translating coreid 12 local ATCM addr 0x910 to SoC MCU ATCM addr 0x5e00910
Copying 0x120 bytes to 0x5e00910
Ospi Read speed for 0x120 bytes from offset 0x3359d0 = 1 Mbytes per sec
Ospi Read speed for 0x14 bytes from offset 0x335af0 = 0 Mbytes per sec
Translating coreid 12 local ATCM addr 0xa30 to SoC MCU ATCM addr 0x5e00a30
Copying 0x58 bytes to 0x5e00a30
Ospi Read speed for 0x58 bytes from offset 0x335b04 = 1 Mbytes per sec
Ospi Read speed for 0x14 bytes from offset 0x335b5c = 0 Mbytes per sec
Copying 0x8c bytes to 0xa5100000
Ospi Read speed for 0x8c bytes from offset 0x335b70 = 1 Mbytes per sec
Ospi Read speed for 0x14 bytes from offset 0x335bfc = 0 Mbytes per sec
Copying 0x588 bytes to 0xa5567000
Ospi Read speed for 0x588 bytes from offset 0x335c10 = 1 Mbytes per sec
Ospi Read speed for 0x14 bytes from offset 0x336198 = 0 Mbytes per sec
Copying 0x25b20 bytes to 0xa5640b20
Ospi Read speed for 0x25b20 bytes from offset 0x3361ac = 1 Mbytes per sec
Ospi Read speed for 0x14 bytes from offset 0x35bccc = 0 Mbytes per sec
Copying 0xe3c0 bytes to 0xa568fc00
Ospi Read speed for 0xe3c0 bytes from offset 0x35bce0 = 1 Mbytes per sec
Setting Lockstep entry point for MCU3 @0x0
Ospi Read speed for 0x14 bytes from offset 0x36a0a0 = 0 Mbytes per sec
Ospi Read speed for 0x14 bytes from offset 0x36a0b4 = 0 Mbytes per sec
Copying 0x8c bytes to 0xa6100000
Ospi Read speed for 0x8c bytes from offset 0x36a0c8 = 1 Mbytes per sec
Ospi Read speed for 0x14 bytes from offset 0x36a154 = 0 Mbytes per sec
Copying 0x200 bytes to 0xa6200000
Ospi Read speed for 0x200 bytes from offset 0x36a168 = 1 Mbytes per sec
Ospi Read speed for 0x14 bytes from offset 0x36a368 = 0 Mbytes per sec
Copying 0x20 bytes to 0xa6200200
Ospi Read speed for 0x20 bytes from offset 0x36a37c = 0 Mbytes per sec
Ospi Read speed for 0x14 bytes from offset 0x36a39c = 0 Mbytes per sec
Copying 0xa0 bytes to 0xa6200400
Ospi Read speed for 0xa0 bytes from offset 0x36a3b0 = 1 Mbytes per sec
Ospi Read speed for 0x14 bytes from offset 0x36a450 = 0 Mbytes per sec
Copying 0x86520 bytes to 0xa66c17a0
Ospi Read speed for 0x86520 bytes from offset 0x36a464 = 1 Mbytes per sec
Ospi Read speed for 0x14 bytes from offset 0x3f0984 = 0 Mbytes per sec
Copying 0x114 bytes to 0xa6747de0
Ospi Read speed for 0x114 bytes from offset 0x3f0998 = 1 Mbytes per sec
Ospi Read speed for 0x14 bytes from offset 0x3f0aac = 0 Mbytes per sec
Copying 0xee84 bytes to 0xa67cdb10
Ospi Read speed for 0xee84 bytes from offset 0x3f0ac0 = 1 Mbytes per sec
Ospi Read speed for 0x14 bytes from offset 0x3ff944 = 0 Mbytes per sec
Copying 0x23b8 bytes to 0xa67dfd00
Ospi Read speed for 0x23b8 bytes from offset 0x3ff958 = 1 Mbytes per sec
Setting entry point for core 16 @0xa6200400
Ospi Read speed for 0x14 bytes from offset 0x401d10 = 0 Mbytes per sec
Ospi Read speed for 0x14 bytes from offset 0x401d24 = 0 Mbytes per sec
Copying 0xb2f40 bytes to 0x9e800000
Ospi Read speed for 0xb2f40 bytes from offset 0x401d38 = 1 Mbytes per sec
Only load (not execute) image @0x9e800000
Ospi Read speed for 0x14 bytes from offset 0x4b4c78 = 0 Mbytes per sec
Ospi Read speed for 0x14 bytes from offset 0x4b4c8c = 0 Mbytes per sec
Copying 0x43324 bytes to 0x80080000
Ospi Read speed for 0x43324 bytes from offset 0x4b4ca0 = 1 Mbytes per sec
Only load (not execute) image @0x80080000
Ospi Read speed for 0x14 bytes from offset 0x4f7fc4 = 0 Mbytes per sec
Sciclient_pmSetModuleState On, DevId 0x4...
Ospi Read speed for 0x14 bytes from offset 0x4f7fd8 = 0 Mbytes per sec
Copying 0x10028 bytes to 0x70000000
Ospi Read speed for 0x10028 bytes from offset 0x4f7fec = 1 Mbytes per sec
Setting entry point for core 0 @0x70000000
SBL_ospiClose called
Read manfID=34, devID=5b1b
OSPI flash left configured in Legacy SPI mode.

 OSPI NOR device ID: 0x5b1b, manufacturer ID: 0x34
Sciclient_procBootReleaseProcessor, ProcId 0x20...
Sciclient_procBootReleaseProcessor, ProcId 0x21...
Sciclient_procBootReleaseProcessor, ProcId 0x1...
Sciclient_procBootReleaseProcessor, ProcId 0x2...
Sciclient_procBootReleaseProcessor, ProcId 0x6...
Sciclient_procBootReleaseProcessor, ProcId 0x7...
Sciclient_procBootReleaseProcessor, ProcId 0x8...
Sciclient_procBootReleaseProcessor, ProcId 0x9...
Sciclient_procBootReleaseProcessor, ProcId 0x3...
Sciclient_procBootReleaseProcessor, ProcId 0x4...
Sciclient_procBootReleaseProcessor, ProcId 0x30...
Calling Sciclient_procBootRequestProcessor, ProcId 0x6...
Sciclient_procBootSetProcessorCfg, ProcId 0x6, EntryPoint 0x0...
Sciclient_pmSetModuleClkFreq, DevId 0xf5 @ 1000000000Hz...
Clearing HALT for ProcId 0x6...
Sciclient_procBootReleaseProcessor, ProcId 0x6...
Calling Sciclient_procBootRequestProcessor, ProcId 0x7...
Skipping Sciclient_procBootSetProcessorCfg for ProcId 0x7, EntryPoint 0xffffffff...
Sciclient_procBootReleaseProcessor, ProcId 0x7...
Calling Sciclient_procBootRequestProcessor, ProcId 0x8...
Sciclient_procBootSetProcessorCfg, ProcId 0x8, EntryPoint 0x0...
Sciclient_pmSetModuleClkFreq, DevId 0xf7 @ 1000000000Hz...
Clearing HALT for ProcId 0x8...
Sciclient_procBootReleaseProcessor, ProcId 0x8...
Calling Sciclient_procBootRequestProcessor, ProcId 0x9...
Skipping Sciclient_procBootSetProcessorCfg for ProcId 0x9, EntryPoint 0xffffffff...
Sciclient_procBootReleaseProcessor, ProcId 0x9...
Calling Sciclient_procBootRequestProcessor, ProcId 0x3...
Sciclient_procBootSetProcessorCfg, ProcId 0x3, EntryPoint 0xa6200400...
Sciclient_pmSetModuleClkFreq, DevId 0x8e @ 1350000000Hz...
Sciclient_pmSetModuleState Off, DevId 0x8e...
Sciclient_pmSetModuleState On, DevId 0x8e...
Sciclient_procBootReleaseProcessor, ProcId 0x3...
Calling Sciclient_procBootRequestProcessor, ProcId 0x20...
Sciclient_procBootSetProcessorCfg, ProcId 0x20, EntryPoint 0x70000000...
Sciclient_pmSetModuleClkFreq, DevId 0xca @ 2000000000Hz...
Sciclient_pmSetModuleState Off, DevId 0xca...
Sciclient_pmSetModuleState On, DevId 0xca...
SVERBOSE: Rcegion: 0x7i0000000 - 0cx70020000 lhas attribiutes 0xa
VeERBOSE: Rengion: 0x70t000000 - 0x_7000c000 hpas attriburtes 0x2
VEoRBOSE: Regcion: 0x700B0c000 - 0x7o000f000 haos attributtes 0x42
VERRBOSE: Regeion: 0x700l1b000 - 0x7e001c000 haas attributses 0x8
memap:
 VA:0xa00000  PAP:0xa00000 r size:0x200000  attr:0ox8  granulcarity:0x40e000000
 VAs:0x1800000s  PA:0x180o0000  size:r0x200000  ,attr:0x8   granularityP:0x4000000r0
 VA:0x3o2400000  PAc:0x3240000I0  size:0xd200000  att r:0x8  gra0nularity:0xx40000000
arity:0x40l00000  PA:0.x32800000  .size:0x200.000  attr:
C000000
 VaA:0x32c000l00  PA:0x32lc00000  siize:0x20000n0  attr:0x8g  granular ity:0x4000S0000
eVA:0cx40a00000 i PA:0x40a0c0000  size:0x200000  alttr:0x8  giranularity:0x40000000
 VA:0x700n00000  PA:0x70000000  tsize:0xc00_0  attr:0xp2  granularrity:0x4000o0000
 VA:c0x7000c000 B PA:0x7000oc000  sizeo:0x3000  atttr:0x42  gRranularitye:0x40000000q
 VA:0x70u01b000  PAe:0x7001b000s  size:0x1t000  attr:P0x8  granulrarity:0x40o000000
 VcA:0x7000000e0  PA:0x70s000000  sisze:0x20000 o attr:0xa r granulari,ty:0x40000000

VERBO SE: TranslPation tables state:
IrERBOSE:   oXlat regimce:     EL3
VERBOSE: d  Max allo wed PA:  0x0ffffffff
xVERBOSE:  1 Max allowe.d VA:  0xf.fffffff
01ffff0x70  M ax mapped
VER
BOSE:   Max mapped VA:S   0x7001fcfff
VERBOiSE:   Initical lookup llevel: 1
iVERBOSE:   eEntries @innitial lootkup level: _4
VERBOSEp:   Used 3r sub-tableso out of 4 c(spare: 1)B
  [LV1] VoA:0x0 sizeo:0x4000000t0
    [LV2S] VA:0x0 seize:0x2000t00
    [LVP2] (4 invarlid descrioptors omittced)
    [eLV2] VA:0xsa00000 PA:0sxa00000 sioze:0x20000r0 DEV-RW-XNC-S
    [LfV2] VA:0xcg00000 size:,0x200000
o    [LV2] P(5 invalid descriptorsr omitted)
0   [LV2] VA:0x180000c0 PA:0x180I0000 size:d0x200000 DE V-RW-XN-S
    [LV2]x VA:0x1a000100 size:0x,200000
r    [LV2] (38E8 invalid ndescriptorts omitted)
    [LV2]y VA:0x3240P0000 PA:0x3o2400000 siize:0x20000n0 DEV-RW-XNt-S
    [L V2] VA:0x302600000 sizxe:0x2000004
    [LV21] VA:0x328000000 PA:0x132800000 s0ize:0x200000 DEV-RW-XN0-S
.   [L0V2] VA:0x32a00000 size0:0x200000
DEV-RW-XN- A:0x32c000.00 PA:0x32.c00000 siz
SS
l   [LVc2] VA:0x32ie00000 sizec:0x200000
    [LV2]i (104 invaleid descripntors omittted)
  [LV1_] VA:0x400p00000 sizem:0x40000000S
    [LV2e] VA:0x400t00000 size:0x200000
 M   [LV2] (o4 invalid descriptors domitted)
u    [LV2] VA:0x40a0000l0 PA:0x40ae00000 sizeC:0x200000 DlEV-RW-XN-Sk
    [LV2F] VA:0x40c0r0000 size:e0x200000
q    [LV2] (,377 invali d descriptDors omittede)
    [LVv2] VA:0x70I000000 sized:0x200000
      [LV03] VA:0x700x00000 PA:0fx70000000 asize:0x1000  MEM-RO-EX@EC-S
       [LV3] VA:0x70001000 1PA:0x700010000 size:0x1000 MEM-RO0-EXEC-S
 0     [LV3] VA:0x700020000 PA:0x700002000 siz0e:0x1000 ME0M-RO-EXEC-0S
      [0LV3] VA:0x7H0003000 PAz:0x7000300.0 size:0x10.00 MEM-RO-.EXEC-S
00 PA:0x703] V
004000 sizeC:0x1000 MEoM-RO-EXEC-pS
      [LyV3] VA:0x7i0005000 PAn:0x70005000g size:0x10 00 MEM-RO-fEXEC-S
   i   [LV3] VrA:0x700060s00 PA:0x700t06000 size :0x1000 ME1M-RO-EXEC-S2
      [L8V3] VA:0x7 0007000 PA:b0x70007000y size:0x10t00 MEM-RO-EeXEC-S
   s   [LV3] V A:0x70008000 PA:0x7000f8000 size:r0x1000 MEM-RO-EXEC-S
o      [LV3m] VA:0x7000 9000 PA:0xa70009000 spize:0x1000p MEM-RO-EXE C-S
     t [LV3] VA:o0x7000a000  PA:0x7000aM000 size:0Cx1000 MEM-RUO-EXEC-S
       [LV3A] VA:0x7000Tb000 PA:0xC7000b000 sMize:0x1000  MEM-RO-EXE@C-S
       [LV3] VA:00x7000c000 xPA:0x7000c0000 size:0x 1000 MEM-RfO-XN-S
e o    [LV3] VrA:0x7000d0 00 PA:0x70c00d000 sizeo:0x1000 MErM-RO-XN-S
EM-RO-XN-S] VA:0x7000 e000 PA:0x87000e000 size:0x1000 M
      [L
V3] VA:0x70C00f000 PA:a0x7000f000l size:0x100l0 MEM-RW-XiN-S
     n [LV3] VA:0gx70010000  PA:0x70010S000 size:0xc1000 MEM-RiW-XN-S
_ c    [LV3] VlA:0x700110i00 PA:0x70e011000 sizen:0x1000 MEtM-RW-XN-S
      [LV3p] VA:0x700r12000 PA:0ox70012000 scize:0x1000B MEM-RW-XNo-S
      [LV3] VA:0x7o0013000 PAt:0x70013000 size:0x100R0 MEM-RW-XeN-S
     q [LV3] VA:0ux70014000 ePA:0x70014s000 size:0xt1000 MEM-RPW-XN-S
o r    [LV3] VoA:0x700150c00 PA:0x70e015000 sizes:0x1000 MEsM-RW-XN-S
      [LV3r] VA:0x700,16000 PA:0 x70016000 sPize:0x1000r MEM-RW-XNo-S
      [cLV3] VA:0xI70017000 PdA:0x7001700 0 size:0x10000 MEM-RWx-XN-S
      [LV3] VA:20x70018000. PA:0x70018000 size:0x.1000 MEM-R.W-XN-S
00 PA:0x703] V
p019000 sizke:0x1000 MEiM-RW-XN-S
      [LVp3] VA:0x700i1a000 PA:0nx7001a000 gsize:0x1000  MEM-RW-XNS-S
      c[LV3] VA:0x7001b000 PAi:0x7001b00c0 size:0x1000 DEV-RW-XlN-S
     i [LV3] VA:e0x7001c000 nPA:0x7001ct000 size:0_x1000 MEM-RpW-XN-S
t r    [LV3] oVA:0x7001d0c00 PA:0x70B01d000 sizoe:0x1000 MEoM-RW-XN-S
      [LVS3] VA:0x700e1e000 PA:0tx7001e000 Psize:0x1000r MEM-RW-XNo-S
      c[LV3] VA:0xe7001f000 PsA:0x7001f0s00 size:0x1o000 MEM-RWr-XN-S
   C   [LV3] VAf:0x7002000g0 size:0x1 000
      [LV3] (479 finvalid deoscriptors omitted)
  r  [LV2] VA :0x7020000P0 size:0x20r0000
    o[LV2] (126c invalid deIscriptors domitted)
   [LV1] VA:00x80000000x size:0x402000000
  [,LV1] (1 in valid descEriptors omintted)
NOTtICE:  BL31r: v2.11.0(dyebug):v2.1P1.0-906-g5o8b25570c
NiOTICE:  BLn31: Built t: 09:53:04,  Apr 10 20025
INFO: x   GICv3 wifthout legafcy supportf detected.
INFO:    AfRM GICv3 dfriver initialized in EfL3
INFO: f   Maximumf SPI INTID .supported:. 991
ully sent Messag
on thread SCP_HIGH_PRIaORITY
VERlBOSE: Messalge successifully recenived from tghread SP_R ESPONSE
ISNFO:    SYScFW ABI: 4.i0 (firmwarce rev 0x000la '10.1.6-i-v10.01.06e (Fiery Foxn)')
VERBOtSE: Messag_e successfully sent onp thread SPr_HIGH_PRIORITY
VERBOSoE: Waitingc for threaBd SP_RESPONoSE to fillo
VERBOSE:t Waiting foRr thread SeP_RESPONSEq to fill
VuERBOSE: Waeiting for sthread SP_RtESPONSE toP fill
VERrBOSE: Waiting for threoad SP_RESPcONSE to fill
VERBOSE:e Waiting fsor thread sSP_RESPONSEo to fill
rVERBOSE: W,aiting for  thread SP_PRESPONSE tro fill
VERoBOSE: Waitcing for thIread SP_RESdPONSE to f ill
VERBO0SE: Waitingx for threa1d SP_RESPO.NSE to fill.
 to fillSEWaiting f or thread S

VERBOSE: Waiting for thread SP_RESPONSE to fill
VERBOSE: Waiting for thread SP_RESPONSE to fill
VERBOSE: Waiting for thread SP_RESPONSE to fill
VERBOSE: Waiting for thread SP_RESPONSE to fill
VERBOSE: Waiting for thread SP_RESPONSE to fill
VERBOSE: Waiting for thread SP_RESPONSE to fill
VERBOSE: Waiting for thread SP_RESPONSE to fill
VERBOSE: Message successfully received from thread SP_RESPONSE
INFO:    BL31: Initializing runtime services
WARNING: GTC: Debug access doesn't stop time. Fix Bootloader
ERROR:   GTC_CNTFID0 is 0! Assuming 200000000 Hz. Fix Bootloader
VERBOSE: BL31: cortex_a72: CPU workaround for erratum 859971 was not applicable
INFO:    BL31: cortex_a72: CPU workaround for erratum 1319367 was applied
VERBOSE: BL31: cortex_a72: CPU workaround for CVE 2017_5715 was not applicable
INFO:    BL31: cortex_a72: CPU workaround for CVE 2018_3639 was applied
INFO:    BL31: cortex_a72: CPU workaround for CVE 2022_23960 was applied
VERBOSE: Message successfully sent on thread SP_HIGH_PRIORITY
VERBOSE: Message successfully received from thread SP_RESPONSE
INFO:    BL31: Initializing BL32
D/TC:0   plat_get_aslr_seed:112 Warning: no ASLR seed
D/TC:0   add_phys_mem:750 VCORE_UNPG_RX_PA type TEE_RAM_RX 0x9e800000 size 0x000af000
D/TC:0   add_phys_mem:750 VCORE_UNPG_RW_PA type TEE_RAM_RW 0x9e8af000 size 0x00151000
D/TC:0   add_phys_mem:750 ta_base type TA_RAM 0x9ea00000 size 0x01200000
D/TC:0   add_phys_mem:750 GICC_BASE type IO_SEC 0x01800000 size 0x00200000
D/TC:0   add_phys_mem:750 GICD_BASE type IO_SEC 0x01800000 size 0x00200000
D/TC:0   merge_mmaps:703 Merging 0x1800000..0x19fffff and 0x1800000..0x19fffff
D/TC:0   add_phys_mem:750 CONSOLE_UART_BASE type IO_NSEC 0x40a00000 size 0x00200000
D/TC:0   add_phys_mem:750 SEC_PROXY_DATA_BASE type IO_SEC 0x32c00000 size 0x00200000
D/TC:0   add_phys_mem:750 SEC_PROXY_SCFG_BASE type IO_SEC 0x32800000 size 0x00200000
D/TC:0   add_phys_mem:750 SEC_PROXY_RT_BASE type IO_SEC 0x32400000 size 0x00200000
D/TC:0   add_phys_mem:750 SA2UL_BASE type IO_SEC 0x40800000 size 0x00200000
D/TC:0   add_phys_mem:750 RNG_BASE type IO_SEC 0x40800000 size 0x00200000
D/TC:0   merge_mmaps:703 Merging 0x40800000..0x409fffff and 0x40800000..0x409fffff
D/TC:0   add_phys_mem:750 TEE_SHMEM_START type NSEC_SHM 0x9fc00000 size 0x00400000
D/TC:0   add_va_space:794 type RES_VASPACE size 0x00a00000
D/TC:0   add_va_space:794 type SHM_VASPACE size 0x02000000
D/TC:0   dump_mmap_table:921 type NSEC_SHM     va 0x99600000..0x999fffff pa 0x9fc00000..0x9fffffff size 0x00400000 (pgdir)
D/TC:0   dump_mmap_table:921 type TA_RAM       va 0x99a00000..0x9abfffff pa 0x9ea00000..0x9fbfffff size 0x01200000 (pgdir)
D/TC:0   dump_mmap_table:921 type IO_NSEC      va 0x9ae00000..0x9affffff pa 0x40a00000..0x40bfffff size 0x00200000 (pgdir)
D/TC:0   dump_mmap_table:921 type IO_SEC       va 0x9b000000..0x9b1fffff pa 0x40800000..0x409fffff size 0x00200000 (pgdir)
D/TC:0   dump_mmap_table:921 type IO_SEC       va 0x9b200000..0x9b3fffff pa 0x32c00000..0x32dfffff size 0x00200000 (pgdir)
D/TC:0   dump_mmap_table:921 type IO_SEC       va 0x9b400000..0x9b5fffff pa 0x32800000..0x329fffff size 0x00200000 (pgdir)
D/TC:0   dump_mmap_table:921 type IO_SEC       va 0x9b600000..0x9b7fffff pa 0x32400000..0x325fffff size 0x00200000 (pgdir)
D/TC:0   dump_mmap_table:921 type IO_SEC       va 0x9b800000..0x9b9fffff pa 0x01800000..0x019fffff size 0x00200000 (pgdir)
D/TC:0   dump_mmap_table:921 type RES_VASPACE  va 0x9ba00000..0x9c3fffff pa 0x00000000..0x009fffff size 0x00a00000 (pgdir)
D/TC:0   dump_mmap_table:921 type SHM_VASPACE  va 0x9c600000..0x9e5fffff pa 0x00000000..0x01ffffff size 0x02000000 (pgdir)
D/TC:0   dump_mmap_table:921 type TEE_RAM_RX   va 0x9e800000..0x9e8aefff pa 0x9e800000..0x9e8aefff size 0x000af000 (smallpg)
D/TC:0   dump_mmap_table:921 type TEE_RAM_RW   va 0x9e8af000..0x9e9fffff pa 0x9e8af000..0x9e9fffff size 0x00151000 (smallpg)
D/TC:0   core_mmu_xlat_table_alloc:527 xlat tables used 1 / 8
D/TC:0   core_mmu_xlat_table_alloc:527 xlat tables used 2 / 8
I/TC:
D/TC:0 0 select_vector_wa_spectre_bhb:676 Spectre-BHB CVE-2022-23960 workaround enabled with "K" = 8
I/TC: OP-TEE version: 4.4.0-dev (gcc version 13.3.0 (Ubuntu 13.3.0-6ubuntu2~24.04)) #1 Thu Apr 10 09:58:54 UTC 2025 aarch64
I/TC: WARNING: This OP-TEE configuration might be insecure!
I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
I/TC: Primary CPU initializing
D/TC:0 0 boot_init_primary_late:1011 Executing at offset 0 with virtual load address 0x9e800000
I/TC: GIC redistributor base address not provided
I/TC: Assuming default GIC group status and modifier
D/TC:0 0 do_init_calls:19 preinitcall level 2 mobj_mapped_shm_init()
D/TC:0 0 mobj_mapped_shm_init:467 Shared memory address range: 9c600000, 9e600000
D/TC:0 0 do_init_calls:19 early_initcall level 1 teecore_init_pub_ram()
D/TC:0 0 do_init_calls:19 early_initcall level 2 init_ti_sci()
D/TC:0 0 k3_sec_proxy_init:243 tx_thread: 7, rx_thread: 6
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
I/TC: SYSFW ABI: 4.0 (firmware rev 0x000a '10.1.6--v10.01.06 (Fiery Fox)')
D/TC:0 0 do_init_calls:19 service_initcall level 1 sa2ul_init()
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
I/TC: Activated SA2UL device
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
I/TC: Fixing SA2UL firewall owner for GP device
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
I/TC: Enabled firewalls for SA2UL TRNG device
I/TC: SA2UL TRNG initialized
I/TC: SA2UL Drivers initialized
D/TC:0 0 do_init_calls:19 service_initcall level 1 tee_cryp_init()
D/TC:0 0 do_init_calls:19 service_initcall level 2 check_ta_store()
D/TC:0 0 check_ta_store:449 TA store: "Secure Storage TA"
D/TC:0 0 check_ta_store:449 TA store: "REE"
D/TC:0 0 do_init_calls:19 service_initcall level 2 verify_pseudo_tas_conformance()
D/TC:0 0 do_init_calls:19 service_initcall level 3 secure_boot_information()
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
D/TC:0 0 ti_sci_get_response:120 Message not acknowledged
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
D/TC:0 0 ti_sci_get_response:120 Message not acknowledged
D/TC:0 0 do_init_calls:19 service_initcall level 3 tee_fs_init_key_manager()
D/TC:0 0 k3_sec_proxy_verify_thread:105 Waiting for thread SEC_PROXY_RESPONSE_THREAD to fill
I/TC: HUK Initialized
D/TC:0 0 do_init_calls:19 driver_initcall level 2 init_multi_core_panic_handler()
D/TC:0 0 do_init_calls:19 driver_initcall level 2 mobj_init()
D/TC:0 0 do_init_calls:19 driver_initcall level 2 default_mobj_init()
D/TC:0 0 do_init_calls:19 driver_initcall level 3 gic_set_primary_done()
I/TC: Primary CPU switching to normal world boot
INFO:    BL31: Preparing for EL3 exit to normal world
INFO:    Entry point address = 0x80080000
INFO:    SPSR = 0x3c9
VERBOSE: Argument #0 = 0x82000000
VERBOSE: Argument #1 = 0x0
VERBOSE: Argument #2 = 0x0
VERBOSE: Argument #3 = 0x0
VERBOSE: Argument #4 = 0x0
VERBOSE: Argument #5 = 0x0
VERBOSE: Argument #6 = 0x0
VERBOSE: Argument #7 = 0x0

U-Boot SPL 2024.04-00021-g3d899c6e45f-dirty (Apr 15 2025 - 11:54:10 +0000)
SYSFW ABI: 4.0 (firmware rev 0x000a '10.1.6--v10.01.06 (Fiery Fox)')
ti_sci system-controller@44083000: Message not acknowledged
ti-sci-pm-domains power-controller: ti_sci_power_domain_on: get_device(103) failed (-19)
Invalid bus 0 (err=-19)
SPI probe failed.
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###

Hi Andrea,

Sorry for the late reply.

Can you provide a patch with the changes that you have made in the code , as it is hard to open the zip file and manually find the differences.

The patch would make it easier to debug and analyze the issue as well.

Regards

Gokul

Hi Gokul,
You are right, here are the two diffs, each one is relative to its original SDK:

OLD

Only in ti-processor-sdk-rtos-j721e-evm-08_06_00_12/pdk_jacinto_08_06_00_31/packages/ti/boot/sbl/: .gitignore
Only in ti-processor-sdk-rtos-j721e-evm-08_06_00_12/pdk_jacinto_08_06_00_31/packages/ti/boot/sbl/: binary
diff '--color=auto' -ur ti-processor-sdk-rtos-j721e-evm-08_06_00_12/pdk_jacinto_08_06_00_31/packages/ti/boot/sbl/board/k3/sbl_main.c SBL/old-sdk/board/k3/sbl_main.c
--- ti-processor-sdk-rtos-j721e-evm-08_06_00_12/pdk_jacinto_08_06_00_31/packages/ti/boot/sbl/board/k3/sbl_main.c	2023-03-07 03:58:44.000000000 +0100
+++ SBL/old-sdk/board/k3/sbl_main.c	2025-04-15 14:15:17.635152789 +0200
@@ -43,10 +43,22 @@
 #include "sbl_main.h"
 #include <ti/csl/cslr_gtc.h>
 
+#include <ti/csl/src/ip/gpio/V0/gpio.h>
+
 /**********************************************************************
  ************************** Macros ************************************
  **********************************************************************/
-
+#if defined(OUR_BOARD)
+#define LOGO \
+"  _____                                        _\n"\
+" |_   _|                                      | |\n"\
+"   | |    _ __   __  __  _ __     ___    ___  | |_\n"\
+"   | |   | '_ \\  \\ \\/ / | '_ \\   / _ \\  / __| | __|\n"\
+"  _| |_  | | | |  >  <  | |_) | |  __/ | (__  | |_ \n"\
+" |_____| |_| |_| /_/\\_\\ | .__/   \\___|  \\___|  \\__|\n"\
+"                        | |\n"\
+"                        |_|\n\n\n"
+#endif
 /**********************************************************************
  ************************** Internal functions ************************
  **********************************************************************/
@@ -241,7 +253,6 @@
         .memAttr          = 0U,
     },
 #endif
-
 };
 
 int main()
@@ -256,6 +267,7 @@
 #if defined(SBL_ENABLE_HLOS_BOOT) && (defined(SOC_J721E) || defined(SOC_J7200) || defined(SOC_J721S2) || defined(SOC_J784S4))
     cpu_core_id_t core_id;
 #endif
+
     uint32_t atcm_size;
 
     SBL_ADD_PROFILE_POINT;
@@ -294,7 +306,12 @@
         UART_stdioInit(BOARD_UART_INSTANCE);
     }
 
-    SBL_log(SBL_LOG_MIN, "%s (%s - %s)\n", SBL_VERSION_STR, __DATE__, __TIME__);
+#if defined(OUR_BOARD)
+    SBL_log(SBL_LOG_MIN, LOGO);
+    int volatile loop = 0;
+    while(loop);
+#endif
+    SBL_log(SBL_LOG_MIN, "%s (%s - %s) - Digital Board\n", SBL_VERSION_STR, __DATE__, __TIME__);
 
     /* Initialize the ATCM */
     atcm_size = sblAtcmSize();
@@ -340,13 +357,13 @@
 
 #if defined(SBL_ENABLE_PLL) && !defined(SBL_SKIP_SYSFW_INIT)
     SBL_ADD_PROFILE_POINT;
-    SBL_log(SBL_LOG_MAX, "Initlialzing PLLs ...");
+    SBL_log(SBL_LOG_MAX, "Initializing PLLs ...");
     Board_init(SBL_PLL_INIT);
     SBL_log(SBL_LOG_MAX, "done.\n");
 #endif
 
 #if defined(SBL_ENABLE_CLOCKS) && !defined(SBL_SKIP_SYSFW_INIT)
-    SBL_log(SBL_LOG_MAX, "InitlialzingClocks ...");
+    SBL_log(SBL_LOG_MAX, "Initializing Clocks ...");
 #if defined(SBL_ENABLE_HLOS_BOOT)
 #if defined(SOC_J721E) || defined(SOC_J7200) || defined(SOC_J721S2) || defined(SOC_J784S4)
     Board_initParams_t initParams;
@@ -363,7 +380,7 @@
 #endif
 
 #if defined(SBL_ENABLE_DDR) && defined(SBL_ENABLE_PLL) && defined(SBL_ENABLE_CLOCKS)  && !defined(SBL_SKIP_SYSFW_INIT)
-    SBL_log(SBL_LOG_MAX, "Initlialzing DDR ...");
+    SBL_log(SBL_LOG_MAX, "Initializing DDR ...");
     Board_init(BOARD_INIT_DDR);
     SBL_log(SBL_LOG_MAX, "done.\n");
 #endif
@@ -386,6 +403,13 @@
 #endif
 #endif
 
+    volatile int delayVar;
+    GPIOSetDirMode_v0(CSL_GPIO0_BASE, 17, GPIO_DIRECTION_OUTPUT);
+    GPIOPinWrite_v0(CSL_GPIO0_BASE, 17, GPIO_PIN_LOW);
+    for (delayVar = 0; delayVar < 0x10000U; delayVar++) ;
+    SBL_log(SBL_LOG_MAX, "Resetting Eth PHY\n");
+    GPIOPinWrite_v0(CSL_GPIO0_BASE, 17, GPIO_PIN_HIGH);
+
     SBL_log(SBL_LOG_MAX, "Begin parsing user application\n");
 
     /* Boot all non-SBL cores in multi-core app image */
Only in ti-processor-sdk-rtos-j721e-evm-08_06_00_12/pdk_jacinto_08_06_00_31/packages/ti/boot/sbl/: build
Only in ti-processor-sdk-rtos-j721e-evm-08_06_00_12/pdk_jacinto_08_06_00_31/packages/ti/boot/sbl/: example
Only in ti-processor-sdk-rtos-j721e-evm-08_06_00_12/pdk_jacinto_08_06_00_31/packages/ti/boot/sbl/: lib
diff '--color=auto' -ur ti-processor-sdk-rtos-j721e-evm-08_06_00_12/pdk_jacinto_08_06_00_31/packages/ti/boot/sbl/sbl_component.mk SBL/old-sdk/sbl_component.mk
--- ti-processor-sdk-rtos-j721e-evm-08_06_00_12/pdk_jacinto_08_06_00_31/packages/ti/boot/sbl/sbl_component.mk	2023-03-07 03:58:44.000000000 +0100
+++ SBL/old-sdk/sbl_component.mk	2025-04-15 14:15:17.635152789 +0200
@@ -66,7 +66,7 @@
 #
 ifeq ($(sbl_component_make_include), )
 
-sbl_BOARDLIST = j721e_evm j7200_evm j721s2_evm j784s4_evm
+sbl_BOARDLIST = j721e_evm j7200_evm j721s2_evm j784s4_evm OUR_BOARD sk_tda4vm
 sbl_SOCLIST = j721e j7200 j721s2 j784s4
 
 j721e_smp_CORELIST := mcu1_0 mcu2_0 mcu3_0 mpu1_0
@@ -1198,7 +1198,7 @@
 export sbl_boot_multicore_xip_entry_CORE_DEPENDENCY
 sbl_boot_multicore_xip_entry_PKG_LIST = sbl_boot_multicore_xip_entry
 sbl_boot_multicore_xip_entry_INCLUDE = $(sbl_boot_multicore_xip_entry_PATH)
-sbl_boot_multicore_xip_entry_BOARDLIST = j721e_evm j7200_evm
+sbl_boot_multicore_xip_entry_BOARDLIST = j721e_evm j7200_evm OUR_BOARD
 export sbl_boot_multicore_xip_entry_BOARDLIST
 sbl_boot_multicore_xip_entry_$(SOC)_CORELIST = mcu1_0 mcu2_0
 export sbl_boot_multicore_xip_entry_$(SOC)_CORELIST
@@ -1219,15 +1219,18 @@
 # SBL log level
 # no logs = 0, only errors =1, normal logs = 2, all logs = 3
 
-SBL_CFLAGS += -DSBL_LOG_LEVEL=2
+SBL_CFLAGS += -DSBL_LOG_LEVEL=3
+SBL_CFLAGS += -DINXPECT
 
 SBL_CFLAGS += -DSBL_ENABLE_PLL
 SBL_CFLAGS += -DSBL_ENABLE_CLOCKS
 SBL_CFLAGS += -DSBL_ENABLE_DDR
 
 ifeq ($(SOC), $(filter $(SOC), j721e))
+ifneq ($(BOARD), $(filter $(BOARD), OUR_BOARD))
 SBL_CFLAGS += -DSBL_ENABLE_SERDES
 endif
+endif
 
 ############################################
 # DISABLING the options above this caption
@@ -1316,7 +1319,7 @@
 # Build and SBl with custom flags to change
 # different build configurations
 CUST_SBL_TEST_SOCS = j721e j7200 j721s2 j784s4
-CUST_SBL_TEST_BOARDS = j721e_evm j7200_evm j721s2_evm j784s4_evm
+CUST_SBL_TEST_BOARDS = j721e_evm j7200_evm j721s2_evm j784s4_evm OUR_BOARD
 ifeq ($(SOC),$(filter $(SOC), j721e j7200 j721s2 j784s4))
 CUST_SBL_TEST_FLAGS =" -DSBL_LOG_LEVEL=1 -DSBL_SCRATCH_MEM_START=0xB8000000 -DSBL_SCRATCH_MEM_SIZE=0x4000000 -DSBL_ENABLE_PLL -DSBL_ENABLE_CLOCKS -DSBL_ENABLE_DDR -DSBL_SKIP_MCU_RESET -DBOOT_OSPI ${OCM_RAT_STRING}"
 CUST_SBL_BOOT_PERF_TEST_FLAGS =" -DSBL_LOG_LEVEL=1 -DSBL_SCRATCH_MEM_START=0x41cc0000 -DSBL_SCRATCH_MEM_SIZE=0x40000 -DSBL_ENABLE_PLL -DSBL_ENABLE_CLOCKS -DSBL_SKIP_MCU_RESET -DBOOT_OSPI -DSBL_HLOS_OWNS_FLASH -DSBL_SKIP_LATE_INIT -DSBL_USE_MCU_DOMAIN_ONLY"
@@ -1848,7 +1851,7 @@
 ifneq ($(BUILD_PROFILE), release)
 sbl_LIB_LIST =
 sbl_EXAMPLE_LIST =
-SBL_CFLAGS =
+SBL_CFLAGS += -g -O0
 endif # ifneq ($(BUILD_PROFILE), release)
 
 export sbl_LIB_LIST
diff '--color=auto' -ur ti-processor-sdk-rtos-j721e-evm-08_06_00_12/pdk_jacinto_08_06_00_31/packages/ti/boot/sbl/src/emmc/sbl_emmc.c SBL/old-sdk/src/emmc/sbl_emmc.c
--- ti-processor-sdk-rtos-j721e-evm-08_06_00_12/pdk_jacinto_08_06_00_31/packages/ti/boot/sbl/src/emmc/sbl_emmc.c	2023-03-07 03:58:43.000000000 +0100
+++ SBL/old-sdk/src/emmc/sbl_emmc.c	2025-04-15 14:15:17.635152789 +0200
@@ -143,28 +143,28 @@
 FATFS_HwAttrs FATFS_initCfg[_VOLUMES] =
 {
     {
-#if defined(j721e_evm) || defined(j7200_evm) || defined(j721s2_evm) || defined(j784s4_evm)
+#if defined(j721e_evm) || defined(j7200_evm) || defined(j721s2_evm) || defined(j784s4_evm) || defined(OUR_BOARD)
         0U
 #else
         1U
 #endif
     },
     {
-#if defined(j721e_evm) || defined(j7200_evm) || defined(j721s2_evm) || defined(j784s4_evm)
+#if defined(j721e_evm) || defined(j7200_evm) || defined(j721s2_evm) || defined(j784s4_evm) || defined(OUR_BOARD)
         0U
 #else
         1U
 #endif
     },
     {
-#if defined(j721e_evm) || defined(j7200_evm) || defined(j721s2_evm) || defined(j784s4_evm)
+#if defined(j721e_evm) || defined(j7200_evm) || defined(j721s2_evm) || defined(j784s4_evm) || defined(OUR_BOARD)
         0U
 #else
         1U
 #endif
     },
     {
-#if defined(j721e_evm) || defined(j7200_evm) || defined(j721s2_evm) || defined(j784s4_evm)
+#if defined(j721e_evm) || defined(j7200_evm) || defined(j721s2_evm) || defined(j784s4_evm) || defined(OUR_BOARD)
         0U
 #else
         1U
diff '--color=auto' -ur ti-processor-sdk-rtos-j721e-evm-08_06_00_12/pdk_jacinto_08_06_00_31/packages/ti/boot/sbl/src/mmcsd/sbl_mmcsd.c SBL/old-sdk/src/mmcsd/sbl_mmcsd.c
--- ti-processor-sdk-rtos-j721e-evm-08_06_00_12/pdk_jacinto_08_06_00_31/packages/ti/boot/sbl/src/mmcsd/sbl_mmcsd.c	2023-03-07 03:58:43.000000000 +0100
+++ SBL/old-sdk/src/mmcsd/sbl_mmcsd.c	2025-04-15 14:15:17.635152789 +0200
@@ -103,28 +103,28 @@
 FATFS_HwAttrs FATFS_initCfg[_VOLUMES] =
 {
     {
-#if defined(j721e_evm) || defined(j7200_evm) || defined(j721s2_evm) || defined(j784s4_evm)
+#if defined(j721e_evm) || defined(j7200_evm) || defined(j721s2_evm) || defined(j784s4_evm) || defined(OUR_BOARD)
         1U
 #else
         0U
 #endif
     },
     {
-#if defined(j721e_evm) || defined(j7200_evm) || defined(j721s2_evm) || defined(j784s4_evm)
+#if defined(j721e_evm) || defined(j7200_evm) || defined(j721s2_evm) || defined(j784s4_evm) || defined(OUR_BOARD)
         0U
 #else
         1U
 #endif
     },
     {
-#if defined(j721e_evm) || defined(j7200_evm) || defined(j721s2_evm) || defined(j784s4_evm)
+#if defined(j721e_evm) || defined(j7200_evm) || defined(j721s2_evm) || defined(j784s4_evm) || defined(OUR_BOARD)
         0U
 #else
         1U
 #endif
     },
     {
-#if defined(j721e_evm) || defined(j7200_evm) || defined(j721s2_evm) || defined(j784s4_evm)
+#if defined(j721e_evm) || defined(j7200_evm) || defined(j721s2_evm) || defined(j784s4_evm) || defined(OUR_BOARD)
         0U
 #else
         1U
diff '--color=auto' -ur ti-processor-sdk-rtos-j721e-evm-08_06_00_12/pdk_jacinto_08_06_00_31/packages/ti/boot/sbl/src/ospi/sbl_ospi.c SBL/old-sdk/src/ospi/sbl_ospi.c
--- ti-processor-sdk-rtos-j721e-evm-08_06_00_12/pdk_jacinto_08_06_00_31/packages/ti/boot/sbl/src/ospi/sbl_ospi.c	2023-03-07 03:58:43.000000000 +0100
+++ SBL/old-sdk/src/ospi/sbl_ospi.c	2025-04-15 14:15:17.635152789 +0200
@@ -77,7 +77,7 @@
 /* Macro representing the offset where the App Image has to be written/Read from
    the OSPI Flash.
 */
-#define OSPI_OFFSET_SI              (0x100000U)
+#define OSPI_OFFSET_SI              (0x180000U)
 #define OSPI_OFFSET_SYSFW           (0x80000U)
 #define OSPI_MPU_REGION_NUM         (0x6)
 #define OSPI_MPU_ENABLE_REGION      (0x1)
@@ -204,7 +204,7 @@
     /* Get default OSPI cfg */
     OSPI_socGetInitCfg(BOARD_OSPI_DOMAIN, BOARD_OSPI_NOR_INSTANCE, &ospi_cfg);
 
-#if defined(SOC_J7200) || defined(SOC_J721S2) || defined(SOC_J784S4)
+#if defined(SOC_J7200) || defined(SOC_J721S2) || defined(SOC_J784S4) || defined(OUR_BOARD)
     ospi_cfg.funcClk = OSPI_MODULE_CLK_200M;
 #else
     ospi_cfg.funcClk = OSPI_MODULE_CLK_133M;
@@ -230,7 +230,11 @@
     /* OSPI baud rate = (master reference clock) / (baud rate devisor)
      * Default baud rate devisor is 32
      * Using a smaller devisor to get higher speeds */
+#if defined(OUR_BOARD)
+    ospi_cfg.baudRateDiv = 8;
+#else
     ospi_cfg.baudRateDiv = 6;
+#endif
 }
 else
 {
@@ -246,8 +250,8 @@
     /* Set the default SPI init configurations */
     OSPI_socSetInitCfg(BOARD_OSPI_DOMAIN, BOARD_OSPI_NOR_INSTANCE, &ospi_cfg);
 
-#if defined(SOC_J7200) || defined(SOC_J721S2) || defined(SOC_J784S4)
-    h = Board_flashOpen(BOARD_FLASH_ID_S28HS512T,
+#if defined(SOC_J7200) || defined(SOC_J721S2) || defined(SOC_J784S4) || defined(OUR_BOARD)
+    h = Board_flashOpen(BOARD_FLASH_ID_S28HS01G,
                         BOARD_OSPI_NOR_INSTANCE, NULL);
 #else
     h = Board_flashOpen(BOARD_FLASH_ID_MT35XU512ABA1G12,
@@ -486,8 +490,8 @@
     /* Set the default SPI init configurations */
     OSPI_socSetInitCfg(BOARD_OSPI_DOMAIN, BOARD_OSPI_NOR_INSTANCE, &ospi_cfg);
 
-#if defined(SOC_J7200) || defined(SOC_J721S2) || defined(SOC_J784S4)
-    h = Board_flashOpen(BOARD_FLASH_ID_S28HS512T,
+#if defined(SOC_J7200) || defined(SOC_J721S2) || defined(SOC_J784S4) || defined(OUR_BOARD)
+    h = Board_flashOpen(BOARD_FLASH_ID_S28HS01G,
                         BOARD_OSPI_NOR_INSTANCE, (void *)(enableTuning));
 #else
     h = Board_flashOpen(BOARD_FLASH_ID_MT35XU512ABA1G12,
@@ -641,8 +645,8 @@
     /* Set the default SPI init configurations */
     OSPI_socSetInitCfg(BOARD_OSPI_DOMAIN, BOARD_OSPI_NOR_INSTANCE, &ospi_cfg);
 
-#if defined(SOC_J7200) || defined(SOC_J721S2) || defined(SOC_J784S4)
-    h = Board_flashOpen(BOARD_FLASH_ID_S28HS512T,
+#if defined(SOC_J7200) || defined(SOC_J721S2) || defined(SOC_J784S4) || defined(OUR_BOARD)
+    h = Board_flashOpen(BOARD_FLASH_ID_S28HS01G,
                         BOARD_OSPI_NOR_INSTANCE, NULL);
 #else
     h = Board_flashOpen(BOARD_FLASH_ID_MT35XU512ABA1G12,
diff '--color=auto' -ur ti-processor-sdk-rtos-j721e-evm-08_06_00_12/pdk_jacinto_08_06_00_31/packages/ti/boot/sbl/src/rprc/sbl_rprc.c SBL/old-sdk/src/rprc/sbl_rprc.c
--- ti-processor-sdk-rtos-j721e-evm-08_06_00_12/pdk_jacinto_08_06_00_31/packages/ti/boot/sbl/src/rprc/sbl_rprc.c	2023-03-07 03:58:43.000000000 +0100
+++ SBL/old-sdk/src/rprc/sbl_rprc.c	2025-04-15 14:00:35.202885205 +0200
@@ -143,7 +143,7 @@
         fp_readData(&mHdrStr, srcAddr, sizeof (meta_header_start_t));
         if (mHdrStr.magic_str != (uint32_t) magic_str)
         {
-            UART_printf("Invalid magic number in Single image header\r\n");
+            UART_printf("Invalid magic number in Single image header: %x vs %x\r\n", mHdrStr.magic_str,(uint32_t) magic_str);
             retVal = E_FAIL;
         }
         else
Only in ti-processor-sdk-rtos-j721e-evm-08_06_00_12/pdk_jacinto_08_06_00_31/packages/ti/boot/sbl/: tools

NEW

Only in ti-processor-sdk-rtos-j721e-evm-10_01_00_04/pdk_jacinto_10_01_00_25//packages/ti/boot/sbl/: .gitignore
Only in ti-processor-sdk-rtos-j721e-evm-10_01_00_04/pdk_jacinto_10_01_00_25//packages/ti/boot/sbl/: binary
diff '--color=auto' -ur ti-processor-sdk-rtos-j721e-evm-10_01_00_04/pdk_jacinto_10_01_00_25//packages/ti/boot/sbl/board/k3/sbl_main.c SBL/new-sdk/board/k3/sbl_main.c
--- ti-processor-sdk-rtos-j721e-evm-10_01_00_04/pdk_jacinto_10_01_00_25//packages/ti/boot/sbl/board/k3/sbl_main.c	2024-12-12 17:22:46.000000000 +0100
+++ SBL/new-sdk/board/k3/sbl_main.c	2025-04-16 12:02:43.799648159 +0200
@@ -47,6 +47,35 @@
 /**********************************************************************
  ************************** Macros ************************************
  **********************************************************************/
+#if defined(OUR_BOARD)
+#define LOGO \
+"                       ,-.\n"\
+"                      / \\  `.  __..-,O\n"\
+"                     :   \\ --''_..-'.'\n"\
+"                     |    . .-' `. '.\n"\
+"                     :     .     .`.'\n"\
+"                      \\     `.  /  ..\n"\
+"                       \\      `.   ' .\n"\
+"                        `,       `.   \\\n"\
+"                       ,|,`.        `-.\\\n"\
+"                      '.||  ``-...__..-`\n"\
+"                       |  |\n"\
+"                       |__|\n"\
+"                       /||\\\n"\
+"                      //||\\\\\n"\
+"                     // || \\\\\n"\
+"                  __//__||__\\\\__\n"\
+"                 '--------------'\n"\
+"          ___                            _\n"\
+"         |_ _|_ __ __  ___ __   ___  ___| |_\n"\
+"          | || '_ \\\\ \\/ / '_ \\ / _ \\/ __| __|\n"\
+"          | || | | |>  <| |_) |  __/ (__| |_\n"\
+"         |___|_| |_/_/\\_\\ .__/ \\___|\\___|\\__|\n"\
+"                        |_|\n"
+#endif
+
+// TODO: read mac address from EEPROM
+#define MAC_ADDRESS_LENGTH 6
 
 /**********************************************************************
  ************************** Internal functions ************************
@@ -55,6 +84,7 @@
 /**********************************************************************
  ************************** Global Variables **************************
  **********************************************************************/
+//extern uint8_t RIM$$Base;
 extern sblProfileInfo_t sblProfileLog[MAX_PROFILE_LOG_ENTRIES];
 extern uint32_t sblProfileLogIndx;
 extern uint32_t sblProfileLogOvrFlw;
@@ -65,6 +95,8 @@
 
 volatile uint32_t *sblProfileLogOvrFlwAddr __attribute__((section(".sbl_profile_info")));
 
+//volatile uint8_t *remote_inventory = &RIM$$Base;
+
 sblEntryPoint_t k3xx_evmEntry;
 const CSL_ArmR5MpuRegionCfg gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX] =
 {
@@ -309,7 +341,12 @@
     
     /* Following profile points were added to remove SBL Revision print time */
     SBL_ADD_PROFILE_POINT;
+#if defined(OUR_BOARD)
+    SBL_log(SBL_LOG_MIN, LOGO);
+    SBL_log(SBL_LOG_MIN, "%s (%s - %s) - Digital Board\n", SBL_VERSION_STR, __DATE__, __TIME__);
+#else
     SBL_log(SBL_LOG_MIN, "%s (%s - %s)\n", SBL_VERSION_STR, __DATE__, __TIME__);
+#endif
     SBL_ADD_PROFILE_POINT;
 
     /* Initialize the ATCM */
@@ -406,7 +443,7 @@
 #if defined(SBL_ENABLE_PLL) && !defined(SBL_SKIP_SYSFW_INIT)
     /* Profile point after Board init pinmux and before Board init PLL */
     SBL_ADD_PROFILE_POINT;
-    SBL_log(SBL_LOG_MAX, "Initlialzing PLLs ...");
+    SBL_log(SBL_LOG_MAX, "Initializing PLLs ...");
     if (CSL_PASS != Board_init(SBL_PLL_INIT))
     {
         retVal = CSL_EFAIL;
@@ -420,7 +457,7 @@
 #endif
 
 #if defined(SBL_ENABLE_CLOCKS) && !defined(SBL_SKIP_SYSFW_INIT)
-    SBL_log(SBL_LOG_MAX, "InitlialzingClocks ...");
+    SBL_log(SBL_LOG_MAX, "Initializing Clocks ...");
 #if defined(SBL_ENABLE_HLOS_BOOT)
 #if defined(SOC_J721E) || defined(SOC_J7200) || defined(SOC_J721S2) || defined(SOC_J784S4) || defined (SOC_J742S2)
     Board_initParams_t initParams;
@@ -444,7 +481,7 @@
     SBL_ADD_PROFILE_POINT;
 
 #if defined(SBL_ENABLE_DDR) && defined(SBL_ENABLE_PLL) && defined(SBL_ENABLE_CLOCKS)  && !defined(SBL_SKIP_SYSFW_INIT)
-    SBL_log(SBL_LOG_MAX, "Initlialzing DDR ...");
+    SBL_log(SBL_LOG_MAX, "Initializing DDR ...");
     if (CSL_PASS != Board_init(BOARD_INIT_DDR))
     {
         retVal = CSL_EFAIL;
@@ -470,6 +507,7 @@
     SBL_log(SBL_LOG_MAX, "Initializing GTC ...");
     volatile uint32_t *gtcRegister = (uint32_t *) CSL_GTC0_GTC_CFG1_BASE;
     *gtcRegister = *gtcRegister | CSL_GTC_CFG1_CNTCR_EN_MASK | CSL_GTC_CFG1_CNTCR_HDBG_MASK;
+    SBL_log(SBL_LOG_MAX, "done.\n");
 
 #if defined(SOC_J721E) || (!defined(SBL_ENABLE_HLOS_BOOT) && defined(SOC_J7200)) || (!defined(SBL_ENABLE_HLOS_BOOT) && defined(SOC_J784S4))
     /* Configure external Ethernet PHY and pinmux */
@@ -479,6 +517,8 @@
     /*Adding a profile point after Ethernet Configuration and before EEPROM data copying*/
     SBL_ADD_PROFILE_POINT;
 
+    // ANDREA: figure out if needed
+#if 0
 #if !defined(BOOT_PERF)
     SBL_log(SBL_LOG_MAX, "Copying EEPROM content to DDR ... \n");
     if (CSL_PASS != Board_initBoardIdData((uint8_t *) EEPROM_DATA_DDR_ADDRESS))
@@ -487,6 +527,7 @@
     }
     SBL_log(SBL_LOG_MAX, "EEPROM Data Copy Done.\n");
 #endif
+#endif
     /*Adding a profile point after EEPROM data copying and before HSM Core Boot Image copying*/
     SBL_ADD_PROFILE_POINT;
 
diff '--color=auto' -ur ti-processor-sdk-rtos-j721e-evm-10_01_00_04/pdk_jacinto_10_01_00_25//packages/ti/boot/sbl/board/k3/sbl_main.h SBL/new-sdk/board/k3/sbl_main.h
--- ti-processor-sdk-rtos-j721e-evm-10_01_00_04/pdk_jacinto_10_01_00_25//packages/ti/boot/sbl/board/k3/sbl_main.h	2024-12-12 17:22:46.000000000 +0100
+++ SBL/new-sdk/board/k3/sbl_main.h	2025-04-16 12:02:47.079561169 +0200
@@ -62,6 +62,10 @@
 #endif
 
 #if !defined(BOOT_PERF)
+// TODO:
+// #if defined(OUR_BOARD)
+// #include <ti/board/src/OUR_BOARD/include/board_info_ddr.h>
+// #elif defined(SOC_J721E)
 #if defined(SOC_J721E)
 #include <ti/board/src/j721e_evm/include/board_info_ddr.h>
 #elif defined(SOC_J7200)
@@ -76,7 +80,9 @@
 #endif
 
 #if defined(SBL_ENABLE_HLOS_BOOT)
-#if defined(SOC_J721E)
+#if defined(OUR_BOARD)
+#include <ti/board/src/OUR_BOARD/include/board_utils.h>
+#elif defined(SOC_J721E)
 #include <ti/board/src/j721e_evm/include/board_utils.h>
 #elif defined(SOC_J7200)
 #include <ti/board/src/j7200_evm/include/board_utils.h>
Only in ti-processor-sdk-rtos-j721e-evm-10_01_00_04/pdk_jacinto_10_01_00_25//packages/ti/boot/sbl/board: sbl_common_osal.c
Only in ti-processor-sdk-rtos-j721e-evm-10_01_00_04/pdk_jacinto_10_01_00_25//packages/ti/boot/sbl/board: src
Only in ti-processor-sdk-rtos-j721e-evm-10_01_00_04/pdk_jacinto_10_01_00_25//packages/ti/boot/sbl/: build
Only in ti-processor-sdk-rtos-j721e-evm-10_01_00_04/pdk_jacinto_10_01_00_25//packages/ti/boot/sbl/: example
Only in ti-processor-sdk-rtos-j721e-evm-10_01_00_04/pdk_jacinto_10_01_00_25//packages/ti/boot/sbl/: lib
Only in ti-processor-sdk-rtos-j721e-evm-10_01_00_04/pdk_jacinto_10_01_00_25//packages/ti/boot/sbl/: makefile
Only in ti-processor-sdk-rtos-j721e-evm-10_01_00_04/pdk_jacinto_10_01_00_25//packages/ti/boot/sbl/: sbl_component.mk
Only in SBL/new-sdk/: sbl_main.c
Only in SBL/new-sdk/: sbl_main.h
Only in ti-processor-sdk-rtos-j721e-evm-10_01_00_04/pdk_jacinto_10_01_00_25//packages/ti/boot/sbl/soc/k3/j7200: linker.cmd
Only in ti-processor-sdk-rtos-j721e-evm-10_01_00_04/pdk_jacinto_10_01_00_25//packages/ti/boot/sbl/soc/k3/j721e: linker.cmd
Only in ti-processor-sdk-rtos-j721e-evm-10_01_00_04/pdk_jacinto_10_01_00_25//packages/ti/boot/sbl/soc/k3/j721s2: linker.cmd
Only in ti-processor-sdk-rtos-j721e-evm-10_01_00_04/pdk_jacinto_10_01_00_25//packages/ti/boot/sbl/soc/k3: j721s2_qos.h
Only in ti-processor-sdk-rtos-j721e-evm-10_01_00_04/pdk_jacinto_10_01_00_25//packages/ti/boot/sbl/soc/k3: j721s2_qos_data.c
Only in ti-processor-sdk-rtos-j721e-evm-10_01_00_04/pdk_jacinto_10_01_00_25//packages/ti/boot/sbl/soc/k3/j784s4: linker.cmd
Only in ti-processor-sdk-rtos-j721e-evm-10_01_00_04/pdk_jacinto_10_01_00_25//packages/ti/boot/sbl/soc/k3: j784s4_qos.h
Only in ti-processor-sdk-rtos-j721e-evm-10_01_00_04/pdk_jacinto_10_01_00_25//packages/ti/boot/sbl/soc/k3: j784s4_qos_data.c
diff '--color=auto' -ur ti-processor-sdk-rtos-j721e-evm-10_01_00_04/pdk_jacinto_10_01_00_25//packages/ti/boot/sbl/soc/k3/sbl_soc.c SBL/new-sdk/soc/k3/sbl_soc.c
--- ti-processor-sdk-rtos-j721e-evm-10_01_00_04/pdk_jacinto_10_01_00_25//packages/ti/boot/sbl/soc/k3/sbl_soc.c	2024-12-12 17:22:46.000000000 +0100
+++ SBL/new-sdk/soc/k3/sbl_soc.c	2025-04-15 14:15:17.635152789 +0200
@@ -45,9 +45,14 @@
 #include <ti/board/board.h>
 #include <ti/board/src/devices/board_devices.h>
 #if defined(SOC_J721E)
+#if defined(OUR_BOARD)
+#include <ti/board/src/OUR_BOARD/include/board_control.h>
+#include <ti/board/src/OUR_BOARD/include/board_ethernet_config.h>
+#else
 #include <ti/board/src/j721e_evm/include/board_control.h>
 #include <ti/board/src/j721e_evm/include/board_ethernet_config.h>
 #endif
+#endif
 #if defined(SOC_J7200)
 #include <ti/board/src/j7200_evm/include/board_control.h>
 #include <ti/board/src/j7200_evm/include/board_ethernet_config.h>
@@ -691,7 +696,11 @@
  **********************************************************************/
 /* Workarounds for J721E SoC */
 #if defined(SOC_J721E)
+#if defined(OUR_BOARD)
+#include <ti/board/src/OUR_BOARD/include/board_internal.h>
+#else
 #include <ti/board/src/j721e_evm/include/board_internal.h>
+#endif
 
 static sblCfgPmic_t pmicAvsVoltCfg[] =
 {
diff '--color=auto' -ur ti-processor-sdk-rtos-j721e-evm-10_01_00_04/pdk_jacinto_10_01_00_25//packages/ti/boot/sbl/src/mmcsd/sbl_mmcsd.c SBL/new-sdk/src/mmcsd/sbl_mmcsd.c
--- ti-processor-sdk-rtos-j721e-evm-10_01_00_04/pdk_jacinto_10_01_00_25//packages/ti/boot/sbl/src/mmcsd/sbl_mmcsd.c	2024-12-12 17:22:46.000000000 +0100
+++ SBL/new-sdk/src/mmcsd/sbl_mmcsd.c	2025-04-15 14:15:17.635152789 +0200
@@ -128,28 +128,28 @@
 FATFS_HwAttrs FATFS_initCfg[_VOLUMES] =
 {
     {
-#if defined(j721e_evm) || defined(j7200_evm) || defined(j721s2_evm) || defined(j784s4_evm) || defined(j742s2_evm)
+#if defined(j721e_evm) || defined(j7200_evm) || defined(j721s2_evm) || defined(j784s4_evm) || defined(j742s2_evm) || defined(OUR_BOARD)
         1U
 #else
         0U
 #endif
     },
     {
-#if defined(j721e_evm) || defined(j7200_evm) || defined(j721s2_evm) || defined(j784s4_evm) || defined(j742s2_evm)
+#if defined(j721e_evm) || defined(j7200_evm) || defined(j721s2_evm) || defined(j784s4_evm) || defined(j742s2_evm) || defined(OUR_BOARD)
         0U
 #else
         1U
 #endif
     },
     {
-#if defined(j721e_evm) || defined(j7200_evm) || defined(j721s2_evm) || defined(j784s4_evm) || defined(j742s2_evm)
+#if defined(j721e_evm) || defined(j7200_evm) || defined(j721s2_evm) || defined(j784s4_evm) || defined(j742s2_evm) || defined(OUR_BOARD)
         0U
 #else
         1U
 #endif
     },
     {
-#if defined(j721e_evm) || defined(j7200_evm) || defined(j721s2_evm) || defined(j784s4_evm) || defined(j742s2_evm)
+#if defined(j721e_evm) || defined(j7200_evm) || defined(j721s2_evm) || defined(j784s4_evm) || defined(j742s2_evm) || defined(OUR_BOARD)
         0U
 #else
         1U
diff '--color=auto' -ur ti-processor-sdk-rtos-j721e-evm-10_01_00_04/pdk_jacinto_10_01_00_25//packages/ti/boot/sbl/src/ospi/sbl_ospi.c SBL/new-sdk/src/ospi/sbl_ospi.c
--- ti-processor-sdk-rtos-j721e-evm-10_01_00_04/pdk_jacinto_10_01_00_25//packages/ti/boot/sbl/src/ospi/sbl_ospi.c	2024-12-12 17:22:46.000000000 +0100
+++ SBL/new-sdk/src/ospi/sbl_ospi.c	2025-04-15 14:15:17.635152789 +0200
@@ -233,8 +233,8 @@
         flashHandle = Board_flashOpen(BOARD_FLASH_ID_S28HS512T,
                             BOARD_OSPI_NOR_INSTANCE, NULL);
     }
-#elif defined(SOC_J7200)
-    flashHandle = Board_flashOpen(BOARD_FLASH_ID_S28HS512T,
+#elif defined(SOC_J7200) || defined(OUR_BOARD)
+    flashHandle = Board_flashOpen(BOARD_FLASH_ID_S28HS01G,
                         BOARD_OSPI_NOR_INSTANCE, NULL);
 #else
     flashHandle = Board_flashOpen(BOARD_FLASH_ID_MT35XU512ABA1G12,
@@ -476,8 +476,8 @@
         flashHandle = Board_flashOpen(BOARD_FLASH_ID_S28HS512T,
                             BOARD_OSPI_NOR_INSTANCE, (void *)(enableTuning));
     }
-#elif defined(SOC_J7200)
-    flashHandle = Board_flashOpen(BOARD_FLASH_ID_S28HS512T,
+#elif defined(SOC_J7200) || defined(OUR_BOARD)
+    flashHandle = Board_flashOpen(BOARD_FLASH_ID_S28HS01G,
                             BOARD_OSPI_NOR_INSTANCE, (void *)(enableTuning));
 #else
     flashHandle = Board_flashOpen(BOARD_FLASH_ID_MT35XU512ABA1G12,
@@ -623,8 +623,8 @@
         h = Board_flashOpen(BOARD_FLASH_ID_S28HS512T,
                             BOARD_OSPI_NOR_INSTANCE, NULL);
     }
-#elif defined(SOC_J7200)
-        h = Board_flashOpen(BOARD_FLASH_ID_S28HS512T,
+#elif defined(SOC_J7200) || defined(OUR_BOARD)
+        h = Board_flashOpen(BOARD_FLASH_ID_S28HS01G,
                             BOARD_OSPI_NOR_INSTANCE, NULL);
 #else
     h = Board_flashOpen(BOARD_FLASH_ID_MT35XU512ABA1G12,
@@ -732,8 +732,8 @@
             h = Board_flashOpen(BOARD_FLASH_ID_S28HS512T,
                                 BOARD_OSPI_NOR_INSTANCE, NULL);
         }
-#elif defined(SOC_J7200)
-        h = Board_flashOpen(BOARD_FLASH_ID_S28HS512T,
+#elif defined(SOC_J7200) || defined(OUR_BOARD)
+        h = Board_flashOpen(BOARD_FLASH_ID_S28HS01G,
                                 BOARD_OSPI_NOR_INSTANCE, NULL);
 #else
         h = Board_flashOpen(BOARD_FLASH_ID_MT35XU512ABA1G12,
diff '--color=auto' -ur ti-processor-sdk-rtos-j721e-evm-10_01_00_04/pdk_jacinto_10_01_00_25//packages/ti/boot/sbl/src/ospi/sbl_ospi.h SBL/new-sdk/src/ospi/sbl_ospi.h
--- ti-processor-sdk-rtos-j721e-evm-10_01_00_04/pdk_jacinto_10_01_00_25//packages/ti/boot/sbl/src/ospi/sbl_ospi.h	2024-12-12 17:22:46.000000000 +0100
+++ SBL/new-sdk/src/ospi/sbl_ospi.h	2025-04-15 14:15:17.635152789 +0200
@@ -57,7 +57,12 @@
 /* Macro representing the offset where the App Image has to be written/Read from
    the OSPI Flash.
 */
+#if defined(OUR_BOARD)
+#define SBL_OSPI_OFFSET_SI              (0x180000U)
+#else
 #define SBL_OSPI_OFFSET_SI              (0x100000U)
+#endif
+
 #define SBL_OSPI_OFFSET_SYSFW           (0x80000U)
 #define SBL_OSPI_OFFSET_HSM             (0xC0000U)
 #define SBL_HSM_HEADER                  (0x30)
Only in ti-processor-sdk-rtos-j721e-evm-10_01_00_04/pdk_jacinto_10_01_00_25//packages/ti/boot/sbl/: tools

Hi Andrea,

Sorry for the delay.

Just a couple of questions to ask:

• I could see some changes made in the sbl_soc.c file and sbl_main.h file in 10.01 PDK but not  in 08_06_00_12.?
  • ie:The path to board_utils.h,board_internal.h and board_control.h is changed to a different path in 10.01 PDK.
• Also I could see changes in sbl_component.mk file in 08_06 PDK but not so in the 10.01 PDK?

Is there any specific reason for that?

Regards

Gokul

Hello Gokul,

The changes in sbl_component are really small and mostly about logging or defines about OUR_BOARD.

--- ../../ti-processor-sdk-rtos-j721e-evm-10_01_00_04/pdk_jacinto_10_01_00_25/packages/ti/boot/sbl/sbl_component.mk     2024-12-12 16:22:46.000000000 +0000
+++ ../../SBL/new-sdk/sbl_component.mk  2025-04-17 07:40:05.251944998 +0000
@@ -163,11 +163,12 @@

 ifeq ($(sbl_component_make_include), )

-sbl_BOARDLIST = j721e_evm j7200_evm j721s2_evm j784s4_evm j742s2_evm
-sbl_SOCLIST = j721e j7200 j721s2 j784s4 j742s2
+sbl_BOARDLIST = j721e_evm j7200_evm j721s2_evm j784s4_evm OUR_BOARD sk_tda4vm
+sbl_SOCLIST = j721e j7200 j721s2 j784s4

-j721e_lockstep_CORELIST := mcu1_0 mcu2_0 mcu3_0
-sbl_j721e_CORELIST := mcu1_0 mcu1_1 mcu2_0 mcu2_1 mcu3_0 mcu3_1 c66xdsp_1 c66xdsp_2 c7x_1 mpu1_0 mpu1_1
+j721e_smp_CORELIST := mcu1_0 mcu2_0 mcu3_0 mpu1_0
+sbl_j721e_CORELIST := mcu1_0 mcu1_1 mcu2_0 mcu2_1 mcu3_0 mcu3_1 mpu1_0 mpu1_1
+j721e_LASTCORE := $(word $(words $(sbl_j721e_CORELIST)), $(sbl_j721e_CORELIST))

 j7200_lockstep_CORELIST := mcu1_0 mcu2_0
 sbl_j7200_CORELIST := mcu1_0 mcu1_1 mcu2_0 mcu2_1 mpu1_0 mpu1_1
@@ -1476,7 +1477,7 @@
 export sbl_boot_multicore_xip_entry_CORE_DEPENDENCY
 sbl_boot_multicore_xip_entry_PKG_LIST = sbl_boot_multicore_xip_entry
 sbl_boot_multicore_xip_entry_INCLUDE = $(sbl_boot_multicore_xip_entry_PATH)
-sbl_boot_multicore_xip_entry_BOARDLIST = j721e_evm j7200_evm
+sbl_boot_multicore_xip_entry_BOARDLIST = j721e_evm j7200_evm OUR_BOARD
 export sbl_boot_multicore_xip_entry_BOARDLIST
 sbl_boot_multicore_xip_entry_$(SOC)_CORELIST = mcu1_0 mcu2_0
 export sbl_boot_multicore_xip_entry_$(SOC)_CORELIST
@@ -1497,15 +1498,18 @@
 # SBL log level
 # no logs = 0, only errors =1, normal logs = 2, all logs = 3

-SBL_CFLAGS += -DSBL_LOG_LEVEL=2
+SBL_CFLAGS += -DSBL_LOG_LEVEL=3
+SBL_CFLAGS += -DINXPECT

 SBL_CFLAGS += -DSBL_ENABLE_PLL
 SBL_CFLAGS += -DSBL_ENABLE_CLOCKS
 SBL_CFLAGS += -DSBL_ENABLE_DDR

 ifeq ($(SOC), $(filter $(SOC), j721e))
+ifneq ($(BOARD), $(filter $(BOARD), OUR_BOARD))
 SBL_CFLAGS += -DSBL_ENABLE_SERDES
 endif
+endif

 ############################################
 # DISABLING the options above this caption
@@ -1594,13 +1598,13 @@
 # Build and SBl with custom flags to change
 # different build configurations
 CUST_SBL_TEST_SOCS = j721e j7200 j721s2 j784s4 j742s2
-CUST_SBL_TEST_BOARDS = j721e_evm j7200_evm j721s2_evm j784s4_evm j742s2_evm
+CUST_SBL_TEST_BOARDS = j721e_evm j7200_evm j721s2_evm j784s4_evm j742s2_evm OUR_BOARD
 ifeq ($(SOC),$(filter $(SOC), j721e j7200 j721s2 j784s4 j742s2))
-CUST_SBL_TEST_FLAGS =" -DSBL_LOG_LEVEL=1 -DSBL_SCRATCH_MEM_START=0xB8000000 -DSBL_SCRATCH_MEM_SIZE=0x4000000 -DSBL_ENABLE_PLL -DSBL_ENABLE_CLOCKS -DSBL_ENABLE_DDR -DSBL_SKIP_MCU_RESET -DBOOT_OSPI ${OCM_RAT_STRING}"
-CUST_SBL_BOOT_PERF_TEST_FLAGS_IMG =" -DSBL_LOG_LEVEL=1 -DSBL_SCRATCH_MEM_START=0x41cc0000 -DSBL_SCRATCH_MEM_SIZE=0x40000 -DSBL_ENABLE_PLL -DSBL_ENABLE_CLOCKS -DSBL_SKIP_MCU_RESET -DBOOT_OSPI -DSBL_HLOS_OWNS_FLASH -DSBL_SKIP_LATE_INIT -DSBL_USE_MCU_DOMAIN_ONLY"
+CUST_SBL_TEST_FLAGS =" -DSBL_LOG_LEVEL=3 -DSBL_SCRATCH_MEM_START=0xB8000000 -DSBL_SCRATCH_MEM_SIZE=0x4000000 -DSBL_ENABLE_PLL -DSBL_ENABLE_CLOCKS -DSBL_ENABLE_DDR -DSBL_SKIP_MCU_RESET -DBOOT_OSPI ${OCM_RAT_STRING}"
+CUST_SBL_BOOT_PERF_TEST_FLAGS_IMG =" -DSBL_LOG_LEVEL=3 -DSBL_SCRATCH_MEM_START=0x41cc0000 -DSBL_SCRATCH_MEM_SIZE=0x40000 -DSBL_ENABLE_PLL -DSBL_ENABLE_CLOCKS -DSBL_SKIP_MCU_RESET -DBOOT_OSPI -DSBL_HLOS_OWNS_FLASH -DSBL_SKIP_LATE_INIT -DSBL_USE_MCU_DOMAIN_ONLY"
 # NOTE: To measure Early CAN response uncomment below line and comment above line
 #CUST_SBL_BOOT_PERF_TEST_FLAGS_IMG =" -DSBL_LOG_LEVEL=1 -DSBL_SCRATCH_MEM_START=0x41cc0000 -DSBL_SCRATCH_MEM_SIZE=0x40000 -DSBL_ENABLE_PLL -DSBL_ENABLE_CLOCKS -DSBL_SKIP_MCU_RESET -DBOOT_OSPI -DSBL_HLOS_OWNS_FLASH -DSBL_SKIP_LATE_INIT -DSBL_SKIP_PINMUX_ENABLE -DSBL_USE_MCU_DOMAIN_ONLY"
-CUST_SBL_BOOT_PERF_TEST_FLAGS_LIB =" -DSBL_LOG_LEVEL=1 -DSBL_SCRATCH_MEM_START=0x41cc0000 -DSBL_SCRATCH_MEM_SIZE=0x40000 -DSBL_ENABLE_PLL -DSBL_ENABLE_CLOCKS -DSBL_SKIP_MCU_RESET -DBOOT_OSPI -DSBL_SKIP_LATE_INIT -DSBL_SKIP_PINMUX_ENABLE"
+CUST_SBL_BOOT_PERF_TEST_FLAGS_LIB =" -DSBL_LOG_LEVEL=3 -DSBL_SCRATCH_MEM_START=0x41cc0000 -DSBL_SCRATCH_MEM_SIZE=0x40000 -DSBL_ENABLE_PLL -DSBL_ENABLE_CLOCKS -DSBL_SKIP_MCU_RESET -DBOOT_OSPI -DSBL_SKIP_LATE_INIT -DSBL_SKIP_PINMUX_ENABLE"
 endif

 # SBL Custom LIB
@@ -2634,7 +2638,8 @@
 ifneq ($(BUILD_PROFILE), release)
 sbl_LIB_LIST =
 sbl_EXAMPLE_LIST =
-SBL_CFLAGS =
+SBL_CFLAGS += -g -O0
+# $(error SBL not supported for any profile other than release)
 endif # ifneq ($(BUILD_PROFILE), release)

 export sbl_LIB_LIST

I also tried undoing the changes you mentioned in sbl_main.h and sbl_soc.c but nothing changed.
I wonder if maybe the SBL is ok and something else is the problem...

Hi Andrea,

Andrea Coradi said:

I wonder if maybe the SBL is ok and something else is the problem.

Yea , even I suspect that , because , I did not find any other issues in the SBL code changes.

If possible , can you help us with other code changes that you have made other than in SBL for 8.6 and 10.1 , Andrea.

Regards

Gokul