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VPIF active video mis-aligned

Other Parts Discussed in Thread: THS8200

I'm driving a THS8200 from DaVinci DM6467 through VPIF and THS8200 drivers, having updated the code to produce a VGA 640x480 output.  I'm getting all my colors and image shape correct, except that the active image is offset on the VGA monitor.  I would think that this would be due to incorrect parameters being sent to the VPIF.  

I've modified vpif_display.c to include an entry for VGA, and in this entry I've configured L3 and L5, which for VPIF are supposed to define the first line of active video and the first line of lower blanking, respectively.  I've confirmed with a trace message in vpif.c that these are the values being sent to the vpifregs.

However, changing L3 and L5 did NOT move the video up or down as I expected.  With a scope, I see that the vertical sync is 2 lines wide (in time).  The active data stops 2 lines before the sync and begins again 41 lines after the sync.  My understanding is that this corresponds to a front porch of 2 and back porch of 41 (inclusive of 8 line borders on the top and bottom of the active image).  I needed to shift the active data earlier by 8 lines in order to match the VGA spec, and doing so ought to make the image on my VGA monitor properly positioned in the vertical.  

Well, I reduced L3 and L5 each by 8, to the current values of 28 and 508 respectively, but the timing on the scope or appearance on the VGA monitor didn't change.  I confirmed with a trace that the desired values were being sent to the vpifregs.  This happens in git/drivers/media/video/davinci/vpif.c function vpif_set_mode_info().  My trace output the correct values and only the correct values, with no other traced calls to vpif_set_mode_info() changing the values to something else.

Either the L3 and L5 are being ignored by the VPIF, or I don't understand what's going on.

I thought the VPIF linux driver and DaVinci hardware would take my buffer from memory and then insert it into the correct place in the data stream according to L3 and L5, such that the data would then be in the proper place relative to the vertical sync to properly position my active video, all per the logical reverse of Figure 5 of the VPIF User's Guide (spruer9d.pdf) which describes capture for a progressive image.

Perhaps my problem is that I don't actually understand the relationship between this Figure 5 and the actual physical vertical sync coming out of the THS8200 pin VS_OUT.  On Figure 5, the "v_sync" line drawn vertically on the left is obviously not a physical sync signal, because high throughout the vertical blanking.  This can't be real because there's no front or back porch.  So this "v_sync" line on Figure 5 must be symbolic, and might represent some state within the VPIF hardware.  But it doesn't represent the actual sync pulse (presumably controlled by an array entry in THS8200.c driver that I modified, that comes out correctly, but that I haven't twiddled to make sure that I'm truly controlling its width).  I also tried separately changing the THS8200.c table entry that ends up going to vfront_porch (aka dtg1_spec_e), but it also did NOT move the relative timing of the vertical sync and active data.

What am I doing or understanding incorrectly?

(FYI, This post relates to http://e2e.ti.com/support/embedded/f/354/p/149609/540734.aspx#540734 .  I'm getting output now by using vpif_display.c array values for eav2sav...vsize of 152,640,1,28,508,0,0,0,525.)

Thanks,

Helmut