SK-AM62P-LP: MCU_I2C0, WKUP_I2C0 connection to PMIC

Hi Jhon,

Jhon Q said:

are both used by TI's BSP for PMIC communication?

The PMIC is assigned to WKUP_I2C on the Linux device tree: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts?h=ti-linux-6.6.y#n851

For the other queries, I'll re-assign to the hardware team to comment. Please allow some time for a response.

Thanks,

Anshu

Hi Jhon,

I suspect this is not for safety application, Can you please confirm.

Regards,

Sreenivasa

Hi 

Thank you for the information, looking forward for you updates and specifically for your advise on my questions Q1,Q2 above

Jhon

Hi Jhon,

Kallikuppa Sreenivasa said:

I suspect this is not for safety application, Can you please confirm.

Could you please confirm if the board is used for safety applications?

Regards,

Sreenivasa

Hi Kallikuppa Sreenivasa,

We are not using the safety variant of the processor.

Jhon

Hi Jhon,

Thank you.

It should be Ok to connect only I2C1 interface. 

I2C1 will be able to additionally perform the tasks that we being performed by I2C2.

Do you have access to the PMIC complete read sheet?

Regards,

Sreenivasa

Hi Sreenivasa,

Thank you for your reply, so just to confirm,

1. MCU_I2C0 lines connected to PMIC pins 35,36 can (PMIC I2C2) be disconnected without implication on PMIC operation such as low power mode support.

2. In terms of SW implementation, currently, only WKUP_I2C lines connected to PMIC pins 1,2 (PMIC I2C1) are defined in the BSP.

Is my understanding correct?

We have the datasheet, the datasheet states: 

"I2C channel 1 (I2C1) is the main channel with access to the registers, which control the configurable power
sequencer, the states and the outputs of power rails, the device operating states and the Error Signal Monitor.
I2C channel 2 (I2C2), which is available through the GPIO1 and GPIO2 pins, is dedicated for accessing the Q&A
Watchdog communication registers. If GPIO1 and GPIO2 are not configured as I2C2 pins, I2C1 can access all
of the registers, including the Q&A Watchdog registers"

Since TI has not defined MCU_I2C0 (I2C2) in the BSP, I assume that this is since Q&A Watchdog registers is not required for standard PMIC operation?

Thank you very much for your support on this,
Jhon

Hi Jhon,

Thank you.

Jhon Q said:

Since TI has not defined MCU_I2C0 (I2C2) in the BSP, I assume that this is since Q&A Watchdog registers is not required for standard PMIC operation?

This is my understanding.

If you need additional information, i can reassign to a software expert.

In parallel, can you please start another thread with the PMIC number (no SOC number in the title) for the PMIC team to support similar query.

Regards,

Sreenivasa

Hi, Kallikuppa Sreenivasa

To close the issue, can you please confirm the below:

Jhon Q said:

1. MCU_I2C0 lines connected to PMIC pins 35,36 can (PMIC I2C2) be disconnected without implication on PMIC operation such as low power mode support.

2. In terms of SW implementation, currently, only WKUP_I2C lines connected to PMIC pins 1,2 (PMIC I2C1) are defined in the BSP.

Is my understanding correct?

Thank you,

Jhon

Hi Jhon,

Jhon Q said:

2. In terms of SW implementation, currently, only WKUP_I2C lines connected to PMIC pins 1,2 (PMIC I2C1) are defined in the BSP.

The device tree file I linked before is designed to support the SK-AM62P-LP EVM. From a schematic standpoint on SK-AM62P-LP, the PMIC's I2C is connected to the SoC's WKUP I2C0, hence the device tree defines the PMIC under the WKUP I2C0 bus.

Best Regards,

Anshu