TDA4VEN-Q1: LPDDR4 design constraint

Furuna Yamamoto

Part Number: TDA4VEN-Q1

Tool/software:

Hi.

Please teach me the details of following constraint.

LP4_DRS5 : Skew across net class DQSx and BYTEx (RSD1 to RSD2 Skew) => Max 25ps
LP4_DRS6 : Propagation delay of each DQS pair must be less than propagation delayDQ/DM. (RSD1 < RSD2) =>Max 150ps

I think that if the skew "LP4_DRS6=150ps" is allowed, "LP4_DRS5" can't be achieved.

Best regards,

Yamamoto.

over 1 year ago

0 Robert Eschler over 1 year ago

TI__Guru 57565 points

The total skew (shortest to longest) across al bits within a byte lane (DQSp/n, DQ[7:0], DM) should be <25ps.

The DQSp/n should be the shortest nets within the byte lane: DQSp/n <= DQ[7:0], DM

0 Furuna Yamamoto over 1 year ago in reply to Robert Eschler

Intellectual 420 points

I understand the meaning of LP4_DRS5 and LP4_DRS6.

Accounding to the constraint "Max. 150ps" of LP_DRS6, please teach me more 1 question.

if LP4_DRS5 is satisfied, wouldn't the LP4_DRS6 constraint be max. 25 ps?

In what cases does the LP4_DRS6 skew to 150ps?

ex. Worst case of LP4_DRS5 and LP4_DRS6

　　DQS0 : 150ps

　　DQ0 : 175ps(BYTE0 max)

　　DQ4 : 160ps(BYTE0 min)

　　==> DQ0(max) - DQS0 = 25ps (LP4_DRS5:OK, LP4_DRS6:OK)

0 Robert Eschler over 1 year ago in reply to Furuna Yamamoto

TI__Guru 57565 points

Yes - if LP4_DRS5 is satisfied, then max skew is 25ps. LP4_DRS6 adds constraint of DQS being shortest within byte lane, and the 150ps isn't very relevant due to LP4_DRS5.

0 Furuna Yamamoto over 1 year ago in reply to Robert Eschler

Intellectual 420 points

Thank you for your explanation.

I understood that the maximum constraint value of LP4_DRS6 "150ps" should be correct to "25ps".

Is that correct?

+1 Robert Eschler over 1 year ago in reply to Furuna Yamamoto

TI__Guru 57565 points

With LP4_DRS5 and LP4_DRS6 combined - yes the max skew across byte will be 25ps with DQSp/n being the shortest nets within byte lane.

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TDA4VEN-Q1: LPDDR4 design constraint