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[FAQ] AM620-Q1: What's the max current input (or output) for SDIO DATA/CMD line?

Part Number: AM620-Q1

Tool/software:

Hi, Dear Expert

I have few question.

(1) What's the max current input and output for SDIO DATA/CMD line?

(2) What's mean for "input leakage current"?

(3) Could we "remove" external PU resistor for SDIO communication? (connect device is WiFi module, not eMMC or SD)

Because of PCBA space limitation. we try to remove external PU resistor, and we found SDIO level become 1.2V.

Does it have side effect?

   

(4) Does SDIO interface support internal PU resistor by register setting? Could we use internal SDIO PU resistor to replace external resistor? 

Thank You Very Much

Gibbs

  • We define output current as IOL and IOH parameters, which is the minimum Low Level Output Current and High Level Output Current for which the device is able to maintain the specified VOL and VOH values. Values defined by these parameters should be considered the maximum current available to a system implementation which needs to maintain the specified VOL and VOH values for attached components.  You will need to use the AM62x IBIS models in a simulation to determine VOL or VOH levels for a specific current.

    We plan to include the following input leakage note in the next revision of the datasheet.  Hopefully, it helps explain what this parameter defines.

    This parameter defines leakage current when the terminal is operating as an input, undriven output, or both input and undriven output,
    without internal pulls enabled.

    Most of the AM62x pins will be turned off after power-up. This means the input buffer is disabled, the output buffer is disabled, and the internal pulls are disabled.  Please reference the Pin Attributes table in the datasheet to see the initial power-up state of each pin. You may need to have external pull resistors on any signals that connect to inputs of attached devices to prevent them from floating until software configures the associated IO cell.

    You can use the AM62x internal pull resistors if an external resistor is not required to hold inputs to a valid state while waiting for software to configure the internal resistors. 

    Regards,
    Paul

  • Hi, Paul

    Thanks your replies.

    one question,

    Do we have minimum Low Level input current and High Level input Current for SDIO?

    Base on "7.8.5 SDIO Electrical Characteristics", I do not see related parameter.

    So I am not sure this is a right question.

    Thank You.

    Gibbs

  • The max input leakage is defined for the two worst-case conditions, which occurs when the voltage applied to the input is 0V or the IO power rail potential. See the test conditions associated with the input leakage current parameter. We do not define input leakage at VIL or VIH, but the leakage current will decrease as the voltage potential applied to the input moves away from either of the two test conditions.

    Regards,
    Paul