TDA4VM: TIDL issue with slice layer

Mladen Knezic

Part Number: TDA4VM

Tool/software:

Hi all,

We experience an issue with a network whose architecture is shown below:

The network is compiled without errors using EdgeAI TIDL Tools v09_01_08_00 (PSDK v09.01.00.06) and executes correctly in PC emulation mode. The output results comparison between floating-point and quantized fixed-point results is illustrated below.

However, when we run the compiled network on the target (TDA4VM), we get different results (see the image below).

We analyzed results for each layer and the result mismatch is observed at the very first convolution layer. It seems like the outputs somehow get corrupted (we suspect it is some synchronization issue related to in-place modification of a data buffer in the slice layer while the same data is used in the second convolution, because the network runs correctly when the Slice layer is removed). We tried to enforce some computation on the slice branch to avoid in-place buffer modification (e.g., by introducing combination of Add and Sub layers before and after the Slice layer), but the issue remains.

We tried to compile the network with the latest EdgeAI TIDL Tools (v10_01_04_00) and run in it with the latest PDSK v10.01.00.04. However, the issue remains even with the latest tools and PSDK version. Is it a known issue and does someone happen to know how to mitigate it?

I attach the ONNX model below so you can reproduce the issue and propose a possible fix.

TestNetwork.zip

Best regards,

Mladen

4 months ago

0 Wen Li 4 months ago

TI__Expert 6881 points

Hello;

Thanks for the question. Which EVM (target) are you using? Could you give me the exact model number.?

Thanks and regards

Wen Li

0 Mladen Knezic 4 months ago in reply to Wen Li

Prodigy 50 points

Hi,

We use SK-TDA4VM Evaluation Board (https://www.ti.com/tool/SK-TDA4VM) as a target.

Best regards,

Mladen

0 Wen Li 4 months ago in reply to Mladen Knezic

TI__Expert 6881 points

Hi Mladen;

Thanks for the info. I have found the same board as you have now.

Could you share your "model_configs.py" file with us?

If not, can you send us your model configure section? Something like the below. So we can run your model based on your ONNX file with the same configuration.

Thank you again

Wen

0 Mladen Knezic 4 months ago in reply to Wen Li

Prodigy 50 points

Hi Wen Li,

Actually, that is not so simple as we adapted the onnxrt_ep.py script so that it can handle input tensors with raw data, so I would need to share with you the whole our infrastructure (which is not possible). What I can prepare for you is an example input data in raw format and pre-compiled TIDL artifacts so you can run inference on your end. I can also capture the detailed log during compilation and send it to you if needed. Please let me know if this would be helpful to you to reproduce the issue.

Best regards,

Mladen

0 Wen Li 4 months ago in reply to Mladen Knezic

TI__Expert 6881 points

Hi Mladen;

That sounds like a good idea. I think it will help us.

Thanks and regards

Wen Li

0 Mladen Knezic 3 months ago in reply to Wen Li

Prodigy 50 points

Hi Wen Li,

I attach the artifacts (including raw data input and full compile log) for the reference.

Note that we managed to resolve the issue by replacing the Slice layer with Conv layer, but this works only on TDA4VM platform. We also test it on the TDA4AL platform (EVM board with this SOM: https://www.ti.com/tool/J721S2XSOMXEVM) and there is the same issue (even when the Slice layer is replaced with the Conv layer).

Best regards,

Mladen

test-network-artifacts.zip

0 Mladen Knezic 3 months ago in reply to Mladen Knezic

Prodigy 50 points

Hello Wen Li,

Are there any news regarding this issue?

Regards,

Mladen

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TDA4VM: TIDL issue with slice layer