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AM6442: MDIO Read data latch timing

Ryuuichi machida
Guru 12650 points
Part Number: AM6442

Tool/software:

Hello,

I would like to confirm which information is correct.

* According to datasheet, there is following two spec.




From datasheet, I understand that MDIO read value at MAC side is latched based on MDC rising edge.
However, according to linux driver for MDIO, it seems that read value is latched based on MDC falling edge.



I'm confusing which information is correct from viewpoint of MDIO read at MAC side (AM64xx).
Could you please give your opinion about this ?

Best Regards,

 

  • 0
    Guru 12650 points

    Hi,

    Could you please give your feedback about this ?

    Best Regards,

  • 0 in reply to Ryuuichi machida
    TI__Mastermind 27300 points

    Hi ,

    Thanks for your query and having patience.

    Which SDK are you working on ?

    Are you working on Linux or RTOS based SDK ?

    Regards

    Ashwani

  • 0 in reply to Ashwani Goel
    Guru 12650 points

    Hello,

    >Which SDK are you working on ? Are you working on Linux or RTOS based SDK ?
    We are using Linux SDK.

    Best Regards,

  • 0 in reply to Ryuuichi machida
    TI__Mastermind 27300 points
    Ryuuichi machida said:
    We are using Linux SDK.

    Thanks for confirmation.

    I am forwarding your query to Linux Ethernet expert.

    Regards

    Ashwani

  • 0 in reply to Ashwani Goel
    TI__Genius 16175 points

    Hello Machida-san, 

    What version of the Linux SDK are you working with? 

    It looks like the Linux driver for MDIO that you are looking at is this driver? https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/drivers/net/mdio/mdio-bitbang.c?h=ti-rt-linux-6.6.y#n56

    If so, this appears to be a general MDIO Linux driver, not specific to any TI specific drivers. In other words, I don't think this mdio-bitbang.c driver was designed with TI SoCs in mind. Instead, for CPSW and PRU_ICSSG Ethernet, we use the davinci_mdio.c driver here https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/drivers/net/ethernet/ti/davinci_mdio.c?h=ti-rt-linux-6.6.y. By default, MDIO is configured in manual mode/bit bang mode.

    Upon a quick glance at the davinci_mdio.c driver, I'm not seeing if it specifically latches data on the falling or rising edge when performing a read. However, it appears that the standard for reading MDIO from the MAC side is likely defined in the IEEE 802.3 Clause 22 standard. From my understanding, it seems that read operations from the MAC side are meant to be latched on the falling edge and for write operations from the MAC side, the PHY is meant to read at the rising edge. I would suggest taking a look at the IEEE 802.3 Clause 22 standard to see if it can clear up your confusion.

    root@am64xx-evm:~# dmesg | grep mdio
[   1.776283] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[   1.810321] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[   1.814004] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[  11.679281] davinci_mdio 300b2400.mdio: Configuring MDIO in manual mode
[  11.749426] davinci_mdio 300b2400.mdio: davinci mdio revision 1.7, bus freq 1000000
[  12.044766] davinci_mdio 300b2400.mdio: phy[15]: device 300b2400.mdio:0f, driver TI DP83869
[  13.457623] am65-cpsw-nuss 8000000.ethernet eth0: PHY [8000f00.mdio:00] driver [TI DP83867] (irq)
[  13.658217] TI DP83869 300b2400.mdio:0f: attached PHY driver (mii_bus:phy_addr=300b2400.mdio:0f,)
[  13.716410] TI DP83869 mdio_mux-0.0:03: attached PHY driver (mii_bus:phy_addr=mdio_mux-0.0:03, i)
root@am64xx-evm:~# uname -a
Linux am64xx-evm 6.6.58-rt45-ti-rt-01780-gc79d7ef3a56f-dirty #1 SMP PREEMPT_RT Wed Nov 27 14:15:26 x
root@am64xx-evm:~#

    Please let us know if you have follow-up questions.

    -Daolin

  • 0 in reply to Daolin Qiu
    Guru 12650 points

    Hello Daolin-san,

    >I would suggest taking a look at the IEEE 802.3 Clause 22 standard to see if it can clear up your confusion.
    I also checked IEEE802.3 Clause 22 to understand this.
    However, it seems that sample timing is defined as rising edge in both case read and write case.

    Quote from IEEE802.3 documentation.

    Case of Read (From viewpoint of MAC)
    When the MDIO signal is sourced by the PHY, it is sampled by the STA synchronously with respect to the rising edge of MDC.

    Case of write (From viewpoint of MAC)
    When the STA sources the MDIO signal, the STA shall provide a minimum of 10 ns of setup time and a minimum of 10 ns of hold time referenced to the rising edge of MDC

    I'm not sure why you mentioned below.

    it seems that read operations from the MAC side are meant to be latched on the falling edge and for write operations from the MAC side, the PHY is meant to read at the rising edge.

    Which document are referring ?

    Best Regards,

  • 0 in reply to Ryuuichi machida
    TI__Genius 16175 points

    Hi Machida-san,

    Ryuuichi machida said:
    I'm not sure why you mentioned below.

    it seems that read operations from the MAC side are meant to be latched on the falling edge and for write operations from the MAC side, the PHY is meant to read at the rising edge.

    Which document are referring ?

    I was referring to https://www.prodigytechno.com/protocols/mdio-management-data-input-output however after reviewing the actual IEEE 802.3 documentation, I think the information provided in this link is probably a wrong interpretation of the read MDIO operation.

    Looking closely at the standard itself: "When the MDIO signal is sourced by the PHY, it is sampled by the STA synchronously with respect to the rising edge of MDC. The clock to output delay from the PHY, as measured at the MII connector, shall be a minimum of 0 ns, and a maximum of 300 ns, as shown in Figure 22–19"

    And https://en.wikipedia.org/wiki/Management_Data_Input/Output indicated "When the PHY drives the MDIO line, the PHY has to provide the MDIO signal between 0 and 300 ns after the rising edge of the clock.[1] Hence, with a minimum clock period of 400 ns (2.5 MHz maximum clock rate) the MAC can safely sample MDIO during the second half of the low cycle of the clock."

    Based on this information, I believe that this means during a read MDIO operation, the MDIO sampled by the MAC should be done at the rising edge of clock. 

    Daolin Qiu said:

    If so, this appears to be a general MDIO Linux driver, not specific to any TI specific drivers. In other words, I don't think this mdio-bitbang.c driver was designed with TI SoCs in mind. Instead, for CPSW and PRU_ICSSG Ethernet, we use the davinci_mdio.c driver here https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/drivers/net/ethernet/ti/davinci_mdio.c?h=ti-rt-linux-6.6.y. By default, MDIO is configured in manual mode/bit bang mode.

    Upon a quick glance at the davinci_mdio.c driver, I'm not seeing if it specifically latches data on the falling or rising edge when performing a read.

    I cannot comment on the mdio-bitbang.c driver which you appear to be referencing. I can only say that the AM64x SoC uses the davinci_mdio.c driver for MDIO operations. Is there a particular functionality issue you are facing with MDIO? What Linux SDK are you working with?

    -Daolin