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Enable Mcasp5 on ti814x

Ishaqe Ahamed
Intellectual 645 points


Hi,

I want to enable mcasp5 in ti814x. I updated the resource structure as follows. But I  found that TI81XX_DMA_MCASP5_AXEVT and TI81XX_DMA_MCASP5_AREVT is not part of the EDMA Default Synchronization Events and found as part of the the multiplexed events (26 & 27).

How  can I set the   TX event .start and .end in the resource struct for multiplexed events ?

static struct resource ti81xx_mcasp5_resource[] = {
 {
  .name = "mcasp5",
  .start = TI81XX_ASP5_BASE,
  .end = TI81XX_ASP5_BASE + (SZ_1K * 12) - 1,
  .flags = IORESOURCE_MEM,
 },
 /* TX event */
 {
  .start = TI81XX_DMA_MCASP5_AXEVT,
  .end = TI81XX_DMA_MCASP5_AXEVT,
  .flags = IORESOURCE_DMA,
 },
 /* RX event */
 {
  .start = TI81XX_DMA_MCASP5_AREVT,
  .end = TI81XX_DMA_MCASP5_AREVT,
  .flags = IORESOURCE_DMA,
 },
};

static struct platform_device ti81xx_mcasp5_device = {
 .name = "davinci-mcasp",
 .id = 5,
 .num_resources = ARRAY_SIZE(ti81xx_mcasp5_resource),
 .resource = ti81xx_mcasp5_resource,
};

 

Regards,

Ishaqe

  • 0
    TI__Expert 5290 points

    Hi,

    First of all make sure that you have the following patch in the kernel http://arago-project.org/git/projects/?p=linux-omap3.git;a=commit;h=d2a0322c461f4bc39c3da6e4ba24fcf11edd3c0b. It fixes a bug in the muxed DMA events.

    To make use of the muxed events you'll also need to modify ti814x_dma_rsv_chans, ti814x_dma_rsv_slots and ti814x_xbar_event_mapping appropriately.

    Regards,

    Vaibhav

     

  • 0 in reply to Vaibhav Bedia
    Intellectual 645 points

    Hi Vaibhav,

    I found that

    static const s16 ti814x_dma_rsv_chans[][2] = {
     /* (offset, number) */
     {0, 2},
     {14, 2},
     {26, 6},
     {48, 4},
     {56, 8},
     {-1, -1}
    };

    static const s16 ti814x_dma_rsv_slots[][2] = {
     /* (offset, number) */
     {0, 2},
     {14, 2},
     {26, 6},
     {48, 4},
     {56, 8},
     {64, 127},
     {-1, -1}
    };

    and

    static struct event_to_channel_map ti814x_xbar_event_mapping[] = {
     /* {xbar event no, Channel} */
     {1, -1},
     {2, -1},
     {3, -1},
     {4, -1},
     {5, -1},
     {6, -1},
     {7, -1},
     {8, -1},
     {9, -1},
     {10, -1},
     {11, -1},
     {12, -1},
     {13, -1},
     {14, -1},
     {15, -1},
     {16, -1},
     {17, -1},
     {18, -1},
     {19, -1},
     {20, -1},
     {21, -1},
     {22, -1},
     {23, -1},
     {24, -1},
     {25, -1},
     {26, -1},
     {27, -1},
     {28, -1},
     {29, -1},
     {30, -1},
     {31, -1},
     {-1, -1}
    };

     

    can you please explain how to configure these structure ?

    Regards,

    Ishaqe

     

  • 0 in reply to Ishaqe Ahamed
    Intellectual 645 points

    Hi Vaibhav,

    I found that

    static const s16 ti814x_dma_rsv_chans[][2] = {
     /* (offset, number) */
     {0, 2},
     {14, 2},
     {26, 6},
     {48, 4},
     {56, 8},
     {-1, -1}
    };

    static const s16 ti814x_dma_rsv_slots[][2] = {
     /* (offset, number) */
     {0, 2},
     {14, 2},
     {26, 6},
     {48, 4},
     {56, 8},
     {64, 127},
     {-1, -1}
    };

    what does offset and number indicate ?

    and

    static struct event_to_channel_map ti814x_xbar_event_mapping[] = {
     /* {xbar event no, Channel} */
     {1, -1},
     {2, -1},
     {3, -1},
     {4, -1},
     {5, -1},
     {6, -1},
     {7, -1},
     {8, -1},
     {9, -1},
     {10, -1},
     {11, -1},
     {12, -1},
     {13, -1},
     {14, -1},
     {15, -1},
     {16, -1},
     {17, -1},
     {18, -1},
     {19, -1},
     {20, -1},
     {21, -1},
     {22, -1},
     {23, -1},
     {24, -1},
     {25, -1},
     {26, -1},
     {27, -1},
     {28, -1},
     {29, -1},
     {30, -1},
     {31, -1},
     {-1, -1}
    };

     

    what does xbar event no and Channel?

    can you please explain how to configure these structure ?

    Regards,

    Ishaqe

  • 0 in reply to Ishaqe Ahamed
    TI__Expert 5290 points

    Hello,

    Have you checked the EDMA driver user guide and the TRM section for EDMA?

    http://processors.wiki.ti.com/index.php/DM81xx_AM38xx_EDMA_Driver_User_Guide

    Regards,

    Vaibhav