AM6422: Does u-boot2024.04 support to enable 2 ethernet ports?

Hello,

First, which type of ethernet are you planning on enabling? I.e. CPSW or PRU_ICSSG ethernet?

If you are using u-boot2024.04, are you using Linux SDK 10.1? Please let us know what SDK version you are using.

Are you currently developing on a custom board using AM6422 or an AM64x EVM?

In the past I have been able to enable the 2nd CPSW ethernet port on an AM62x with only DTS changes. This was back on uboot2023.04. I haven't tried on u-boot2024.04 and AM64x devices before. It may be worth trying to change the U-boot DTS first and see if there are issues.

I've referenced the DTS changes I made to enable the 2nd CPSW ethernet port on AM62x below as a reference in case you are planning to enable CPSW ethernet on your AM64x board. 

 arch/arm/dts/k3-am62x-sk-common-u-boot.dtsi | 35 +++++++++++++++++++--
 1 file changed, 33 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/k3-am62x-sk-common-u-boot.dtsi b/arch/arm/dts/k3-am62x-sk-common-u-boot.dtsi
index 4265b434..0b093edb 100644
--- a/arch/arm/dts/k3-am62x-sk-common-u-boot.dtsi
+++ b/arch/arm/dts/k3-am62x-sk-common-u-boot.dtsi
@@ -146,7 +146,7 @@
 	reg-names = "cpsw_nuss", "mac_efuse";
 	/delete-property/ ranges;
 	/* This is WA because MDIO driver is not DM enabled */
-	pinctrl-0 = <&main_mdio1_pins_default &main_rgmii1_pins_default>;
+	pinctrl-0 = <&main_mdio1_pins_default &main_rgmii1_pins_default &main_rgmii2_pins_default>;
 	bootph-pre-ram;
 
 	cpsw-phy-sel@04044 {
@@ -157,9 +157,40 @@
 };
 
 &cpsw_port2 {
-	status = "disabled";
+	phy-mode = "rgmii-rxid";
+	phy-handle = <&cpsw3g_phy1>;
+	bootph-pre-ram;
 };
 
+&cpsw3g_mdio {
+	cpsw3g_phy1: ethernet-phy@1 {
+		reg = <1>;
+		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+		ti,min-output-impedance;
+	};
+};
+
+&main_pmx0 {
+	main_rgmii2_pins_default: main-rgmii2-pins-default {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */
+			AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */
+			AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */
+			AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */
+			AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */
+			AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */
+			AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */
+			AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */
+			AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */
+			AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */
+			AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */
+			AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */
+		>;
+	};
+};
+
+
 &main_bcdma {
 	bootph-pre-ram;
 	reg = <0x00 0x485c0100 0x00 0x100>,
-- 
2.34.1

-Daolin

Hi Daolin,

1. I want to enable 2 CPSW ethernet ports. the first CPSW works well in u-boot. 

2. I am using u-boot2024.04, but not using  Linux SDK 10.1.  I am using VxWorks7, not linux.

3.we are currently developing on a custom board uing AM6422. And we reffer to the hardware desing of AM64x EVM board(TMDS64EVM) and SK-AM64B

4.referring to  I have completed the DTS changes as flows, but the second CPSw is not probed through "dm tree" command info.

&cpsw_port2 {
+ bootph-all;
phy-mode = "rgmii-rxid";
- phy-handle = <&cpsw3g_phy3>;
+ phy-handle = <&cpsw3g_phy1>;
};

&cpsw3g_mdio {
@@ -662,6 +512,14 @@
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
+
+ 
+ cpsw3g_phy1: ethernet-phy@1 {
+ bootph-all;
+ reg = <1>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
};

Hello, 

?? ? said:

- phy-handle = <&cpsw3g_phy3>;
+ phy-handle = <&cpsw3g_phy1>;

?? ? said:

+ cpsw3g_phy1: ethernet-phy@1 {
+ bootph-all;
+ reg = <1>;

In your custom board, is the Ethernet PHY address for the 2nd CPSW port 1 or 3? Please note that on the TMDS64EVM, the PHY on 2nd CPSW port is actually at address 3 if I remember correctly.

Are you able to see the 2nd CPSW port with "net list" command in U-boot?

-Daolin

Are you able to see the 2nd CPSW port with "net list" command in U-boot? --- no

In my custom board, the 1st CPSW port is 1, the 2nd is 2.

great, thanks a lot, I will compare the DTS. If I have any question, I will contact to you.