if any one knows the answer,plz help...
thank u.
HI Richard：
First of all,I want 2 thanks u 4 you reply.and this is the mail really makes me happy and to find some hope when debug the OMAP 3530.And some of the message are very helpful.
Sorry for not specifying the type which I am using:OMAP35x Applications Processor.
The mark on the BGA is really too small for me to read them out,but I think the functions of the DPLLs inside the chip is pretty much same?
Yesterday I read the TRM again and again finally find myself some useful informations,but I am not quite sure about my understanding,and go along with the mail I try to analyze…
-a- At power on reset the fast-sysclk (12-34.4)MHz is supplied on DPLL1_AWON_FCLK. This goes into MPU-DPLL and is what ROM code will start executing on. ROM code will lock DPLL to some frequency (based on boot image) and run. The ROM dispatches to 1st stage customer loader which typically relocks the DPLL to yet a higher rate.
This is quote from Richard,but how to chose the DPLL1_AWON_FCLK and DPLL1_FCLK?When power up?x-load tells us all the functions from prcm_init() to set the register to a lock mode after set the MN value and freqsel,but under which clock,MPU is running before DPLL locks?
Yes,it is DPLL_ALOWN_FCLK,as the TRM said,the way to omit the DPLL1_FCLK is the register CM_CLKSEL1_PLL_MPU reset value,when M value is 0000,DPLL1 is set to bypass mode,which is called MN bypass mode.{Notes 1}.if MN Bypass mode is worked on,the DPLL1 choose to accept the DPLL_ALOWN_FCLK for low frequency bypass clock.
Is my understanding correctly?
Notes 1：
I think the bypass mode is not only suits for low-frequency bypass clock but also high-frequency bypass clock.plz see the picture-dpll in the attachment.
If a clock is choosed to accept meanwhile another is omitted.the clock which is accepted can be ranged from 100MHz to 1GMHz.if lower than 600MHz is low-power bypass mode? Is my understanding correctly?
-b- For a power optimization a customer might want to run the system in a dpll-bypass configuration. In this form the CORE DPLL output can be routed into MPU and DSP on DPLLx_FCLK. If so programmed the entire system can run at bypass frequency. This kind of think was typically done for low power MP3 usecase. (thanks for your information) The advantage of this is you can stop non-used DPLLs and regain ~3mA per bypassed DPLL. This value is significant against a optimized low power use case. If your system power consumption is very high then taken this kind of optimization doesn’t matter much relatively speaking.
Sorry,I don not have the instruments to measure the exactly the power consumption at home.I just want to try to get the understanding of the omap 3530,and running some apps on the linux OS.but when reading the PM codes,find myself difficult to understand.
Bypass mode is has another way to work :LP mode.and :MN bypass mode above. What is the diffecence?
This is quote from Richard,I read the TRM for more information and if the DPLLs are set to low-power bypass mode,the opp(voltage supply) is accordingly changed?is that so?if the frequency is lower than 600 MHz,it is automatically changed to low-power bypass mode(LP Mode)?Hardware can tell the difference between >600MHz or <600MHz?
What is freqsel?what effect will the input clock cause? feedback frequency from N output rate is traced by pll,this will make the output into a stable reange.why we must set the freqsel before the lock state,while bypass mode(MN Mode) not required?