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SK-AM62-LP: How to modify Vref CA taining range?

Maurice Lu
Prodigy 120 points
Part Number: SK-AM62-LP

Tool/software:

Hi team, 

I found these two registers in TRM:

PI_CALVL_VREF_INITIAL_START_POINT

PI_CALVL_VREF_INITIAL_STOP_POINT

What is the range value of HEX in these two registers?

How should I modify if I want to increase the training range?

(ex: DDRSS_PI_207_DATA 0x321E3200)

Thanks.

Maurice

  • 0
    TI__Guru* 86180 points

    Hi Maurice, the start and stop points are in the MSBs of the register you show:   0x321E3200

    Red is stop point, Green is start point. Note these are calculated based on the driver and ODT settings for CA.  Why do you need to change them?  We have an errata item which restricts this range (this is why it is being calculated), otherwise the CA training algorithm may hang.  

    Regards,

    James

  • 0 in reply to JJD
    Prodigy 120 points

    Hi James,

    We have new LPDDR4 product, we want to test with different training range and step to study charateristic.

    Where canI find the errata item? Is it available?

    Additional question, are there registers define the CA to CLK training range and step?

    Thanks for the reply.

    Maurice

  • +1 in reply to Maurice Lu
    TI__Guru* 86180 points

    Hi Maurice, the errata will show up in next versions of errata docs.  For now, here is a preliminary version:

    What do you mean by CA to CLK training range?  Do you mean the slave delays to help align CA to CLK?  There aren't any adjustable registers for this function.  The training process will perform a per-bit deskew across a 300ps delta to for the addr/ctrl as well as data busses.

    Regards,

    James

  • 0 in reply to JJD
    Prodigy 120 points

    Hi James,

    Thanks for the answer, this totally solves my question.

    Maurice