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AM67: AM67x PCIe external source clock

Rich Chen
Expert 4170 points
Part Number: AM67

Tool/software:

Champs, 

There are three errata for AM67x PCIe.

i.2242, i.2243 and i.2326

For i.2242, customer is wondering whether they can use clock source generate from AM67x if they claim support PCIe gen 2 only (not support Gen 3, 8Gbps). Customer will not use PCIe Gen 3 device either.  

The purpose is not using external source clock for production to save cost.  

For i.2243 and i.2326, one is for clock gating and another is for PCIe SSC support. 

If not considering these two items, will we recommend adding external source clock for PCIe? (option 4 for i.2242) 

Please comment on this ASAP since customer is doing PCB revising and need to decide adding external 100Mhz clock source or not.  

 

BR, Rich

  • 0
    TI__Guru 64410 points

    Hi,

    It’s a long weekend, so kindly expect a response early next week.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    TI__Expert 4170 points

    Sudheer, 

    Could we have team's feedback on this ASAP? 

    Customer is about to fix their schematic design for PCB and need to know our recommendation. 

    One additional question for SW, 

    Does current SDK support outputting PCIe clock from AM67x and using external clock source respectively?

    By adding external clock source, will there be any software change/setting required? 

    BR, Rich

  • 0 in reply to Rich Chen
    TI__Guru 51193 points

    Hi Rich,

    For SK-AM67/J722S-EVM specifically, the board does not have an external clock source and SoC is generating and providing the PCIe reference clock. Below is from our public schematics files:

    As you may notice, there are some DNI (Do Not Install) resistors that can be installed to connect to external clock from CLKGEN_SERDES1_REFCLK_P/N and removing the R3, R4, C1, C2 will disconnect clock from SoC to connector.

    So it should be possible to use internal or external clock.

    Software will mainly be devicetree changes. Default devicetree for J722S/AM67 is internal. Using external clock source will have differences. 

    As for the erratas, I have not encountered the erratas personally when using some PCIe cards from well-known vendors, but I have seen customers in the past with FPGA or network switch seemingly encounter issues due to errata (although, we have not gotten confirmation whether the erratas were the cause of the issues).

    Regards,

    Takuma

  • 0 in reply to Takuma Fujiwara
    TI__Expert 4170 points

    Takuma, 

    Thanks for the answers, 

    Therefore, i2242 will not be problem if not support 8GT/sec data rate (not support GEN 3).

    In this case, customer can keep using internal clock for production.

    BR, Rich