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AM6442: How to keep CS enabled between bytes of MCSPI transaction

Part Number: AM6442


Tool/software:

I have an MCSPI transaction that I am performing. The data size is 8 bits, and i want to transmit 3 consecutive frames without disabling CS in between them. This is required by the hardware.

I try setting csDisable = FALSE, which seems to do nothing. I have a multi-controller SPI setup. Channel 0 does not require this and works fine, but channel 1 requires this and is not working. Im using the LLD not the HLD. 

MCSPI config:

  • Hi Shane,

    I currently know that csDisable should do the job. When it is set to False, it should just work fine and be enabled until its set as True for the last transaction.

    Allow me sometime to check this on my setup via probing on the logic analyzer.

    Regards,

    Vaibhav

  • For clarity this is multi-channel mode. Two spi devices. csDisable didnt seem to do anything. I see in the driver it seems to only be used with 

    MCSPI_CH_MODE_SINGLE
  • Hi Shane,

    I am checking how and where the macro MCSPI_CH_MODE_SINGLE is used and in which context to help you better.

    The results for Single Controller are promising:

    Transaction Behaviour, Single Controller:

    HLD Enabled:

    10 transactions with csDisable = TRUE:

    10 transactions with csDisable = FALSE and TRUE for last transaction:

    Using LLD:

    10 transactions with csDisable = TRUE:

    10 transactions with csDisable = FALSE and TRUE for last transaction:

    For Multi Controller mode, I see a whole lot of chip selects in the transaction. Let me see why this could be happening.

    Regards,

    Vaibhav

  • Hi Shane,

    I have seen that for Multi Controller, the Chip Select goes down for every single byte transferred.

    This is happening as the driver has a check for Single Controller mode and not for Multi Controller mode.

    I am assuming these are automatic chip selects for every single byte getting transferred.

    I am checking this with the development team as to what fix can be implemented in the drivers so that the behaviour is consistent across Single and Multi Controller MCSPI modes.

    Allow me sometime to get back on this after I have done a round of internal discussion.

    Additional Note:

    There is a chip select for a byte sent, and this has been confirmed from the code and waveform using logic analyzer. So you see the below snippet of waveform:

    It is basically a transfer of a byte(value 18) and the chip select is automatic for this transfer and is not touched in the drivers.

    In the drivers as soon as the API 

    CSL_REG32_WR(baseAddr + MCSPI_CHTX(chNum), txData); 

    is called we see the behaviour as shown for a byte(value 18) transfer.

    Regards,

    Vaibhav

  • Hi Shane,

    As I was going through the drivers for MCSPI, I observed that it is expected behaviour for CS to be controller by hardware and not by software when configuring multiple channels for the Controller.

    Please find the below API snippet, line number 2224:

    Regards,

    Vaibhav

  • Yeah i saw that in the code and in the datasheet that the behavior is differnet between single and multi controller setups, but since this is very limiting as to what devices we can use, was wondering if there is a hardware config to turn keep CS asserted across bytes

  • Hi Shane,

    I have even tried at register level, the changes do not seem to manually control the CS, it is still being controlled by HW.

    Could you please go ahead and create another E2E thread, where you ask about disabling the CS by modifying the hardware.

    Marking this thread closed as from SW end I have tried different possibilities as well.

    Regards,

    Vaibhav