AM6422: linux freertos gpio_interrupt

Hello,

Just for reference, its not possible to share peripherals between different cores. Refer to the Multicore Academy for more information: https://dev.ti.com/tirex/explore/node?node=A__AaRdsK4zRjlChfPY2v0AhQ__AM64-ACADEMY__WI1KRXP__LATEST

wanglili 王 said:

However, when using Linux to boot the R5F, the external interrupts become unresponsive

Can you explain this further?

Thanks,

Anshu

Hello，

    I didn't explain it clearly, so let me rephrase it. In my real-time core program, I'm using an external interrupt. When the real-time core program runs independently, the external interrupt can enter normally. However, when I switch to having the non-real-time core boot and start the real-time core, and with the external interrupt hardware present, I found through debugging the real-time core in the CCS development environment that the interrupt does not enter the real-time core's interrupt function. The resource configurations in the Linux device tree do not involve the external interrupt pins used by the real-time core. Throughout the operation of the real-time core, I noticed that only the function intended for the external interrupt does not execute, while the timer interrupt function can enter normally.

After the non-real-time core boots and starts the real-time core, when debugging under CCS using a JTAG development machine, I checked the 0x60005c register and confirmed that a falling-edge event on the corresponding pin has occurred. However, the relevant external interrupt source was never read in the HwiP_getIRQ(&intNum); function, resulting in the external interrupt function never being entered. I hope to get your assistance with this issue.

Hello,

I'll review this information and get back to you.

Thanks,

Anshu

Hello，

    Is there anything news？I can provide my code.

5543.example.rar

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
 */

/dts-v1/;

#include <dt-bindings/phy/phy.h>
#include <dt-bindings/mux/ti-serdes.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include "k3-am642.dtsi"

/ {
	compatible =  "ti,am642-evm", "ti,am642";
	model = "Texas Instruments AM642 EVM";

	chosen {
		stdout-path = "serial2:115200n8";
		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
	};

	aliases {
		ethernet2 = &icssg0_emac0;
		ethernet3 = &icssg0_emac1;
	};
	memory@80000000 {
		device_type = "memory";
		/* 2G RAM */
		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;

	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		secure_ddr: optee@9e800000 {
			reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
			alignment = <0x1000>;
			no-map;
		};

		main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa0000000 0x00 0x100000>;
			no-map;
		};

		main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa0100000 0x00 0xf00000>;
			no-map;
		};

//		main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
//			compatible = "shared-dma-pool";
//			reg = <0x00 0xa1000000 0x00 0x100000>;
//			no-map;
//		};
//
//		main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
//			compatible = "shared-dma-pool";
//			reg = <0x00 0xa1100000 0x00 0xf00000>;
//			no-map;
//		};

		main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa2000000 0x00 0x100000>;
			no-map;
		};

		main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa2100000 0x00 0xf00000>;
			no-map;
		};

//		main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
//			compatible = "shared-dma-pool";
//			reg = <0x00 0xa3000000 0x00 0x100000>;
//			no-map;
//		};
//
//		main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
//			compatible = "shared-dma-pool";
//			reg = <0x00 0xa3100000 0x00 0xf00000>;
//			no-map;
//		};

		mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa4000000 0x00 0x100000>;
			no-map;
		};

		mcu_m4fss_memory_region: m4f-memory@a4100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa4100000 0x00 0xf00000>;
			no-map;
		};

		rtos_ipc_memory_region: ipc-memories@a5000000 {
			reg = <0x00 0xa5000000 0x00 0x00800000>;
			alignment = <0x1000>;
			no-map;
		};
	};

		icssg0_eth: icssg0-eth {
			compatible = "ti,am642-icssg-prueth";
			pinctrl-names = "default";
			pinctrl-0 = <&icssg0_rgmii1_pins_default &icssg0_rgmii2_pins_default>;
			
			sram = <&oc_sram>;
			ti,prus = <&pru0_0>, <&rtu0_0>, <&tx_pru0_0>, <&pru0_1>, <&rtu0_1>, <&tx_pru0_1>;
			firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
			                "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
			                "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
			                "ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
			                "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
			                "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
			
			ti,pruss-gp-mux-sel = <2>,      /* MII mode */
			                      <2>,       
			                      <2>,       
			                      <2>,      /* MII mode */
			                      <2>,       
			                      <2>;       
			
			mii-g-rt = <&icssg0_mii_g_rt>;
			mii-rt = <&icssg0_mii_rt>;
			iep = <&icssg0_iep0>,  <&icssg0_iep1>;
			
			interrupt-parent = <&icssg0_intc>;
			interrupts = <24 0 2>, <25 1 3>;
			interrupt-names = "tx_ts0", "tx_ts1";
			
			dmas = <&main_pktdma 0xc100 15>, /* egress slice 0 */
			       <&main_pktdma 0xc101 15>, /* egress slice 0 */
			       <&main_pktdma 0xc102 15>, /* egress slice 0 */
			       <&main_pktdma 0xc103 15>, /* egress slice 0 */
			       <&main_pktdma 0xc104 15>, /* egress slice 1 */
			       <&main_pktdma 0xc105 15>, /* egress slice 1 */
			       <&main_pktdma 0xc106 15>, /* egress slice 1 */
			       <&main_pktdma 0xc107 15>, /* egress slice 1 */
			       <&main_pktdma 0x4100 15>, /* ingress slice 0 */
			       <&main_pktdma 0x4101 15>, /* ingress slice 1 */
			       <&main_pktdma 0x4102 0>, /* mgmnt rsp slice 0 */
			       <&main_pktdma 0x4103 0>; /* mgmnt rsp slice 1 */
			dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
			            "tx1-0", "tx1-1", "tx1-2", "tx1-3",
			            "rx0", "rx1",
			            "rxmgm0", "rxmgm1";
			
			icssg0_emac0: ethernet-mii0 {
							status = "okay";
							phy-handle = <&icssg0_phy1>;
        			phy-mode = "rgmii-rxid";
			        syscon-rgmii-delay = <&main_conf 0x4110>;
			        /* Filled in by bootloader */
			        local-mac-address = [00 00 00 00 00 00];
			};
			
			icssg0_emac1: ethernet-mii1 {
							status = "okay";
							phy-handle = <&icssg0_phy2>;
        			phy-mode = "rgmii-rxid";
			        syscon-rgmii-delay = <&main_conf 0x4114>;
			        /* Filled in by bootloader */
			        local-mac-address = [00 00 00 00 00 00];
			};
     };
com8_ls_en: regulator-1 {
		compatible = "regulator-fixed";
		regulator-name = "com8_ls_en";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
		regulator-boot-on;
		pinctrl-0 = <&main_com8_ls_en_pins_default>;
		pinctrl-names = "default";
		gpio = <&main_gpio1 61 GPIO_ACTIVE_LOW>;
	};
wlan_en: regulator-2 {
		/* output of SN74AVC4T245RSVR */
		compatible = "regulator-fixed";
		regulator-name = "wlan_en";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		enable-active-high;
		pinctrl-0 = <&main_wlan_en_pins_default>;
		pinctrl-names = "default";
		vin-supply = <&com8_ls_en>;
		gpio = <&main_gpio0 31 GPIO_ACTIVE_HIGH>;
	};	
//	leds {
//		compatible = "gpio-leds";
//		pinctrl-names = "default";
//		pinctrl-0 = <&usr_led_pins_default>;
//
//		led-0 {
//			label = "am64-evm:green:heartbeat";
//			gpios = <&main_gpio1 44 GPIO_ACTIVE_HIGH>;
//			linux,default-trigger = "heartbeat";
//			function = LED_FUNCTION_HEARTBEAT;
//			default-state = "off";
//		};
//	};
};
&main_r5fss0_core0 {
	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
	memory-region = <&main_r5fss0_core0_dma_memory_region>,
			<&main_r5fss0_core0_memory_region>;
};

//&main_r5fss0_core1 {
//	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
//	memory-region = <&main_r5fss0_core1_dma_memory_region>,
//			<&main_r5fss0_core1_memory_region>;                	
//};

&main_r5fss1_core0 {
	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
	memory-region = <&main_r5fss1_core0_dma_memory_region>,
			<&main_r5fss1_core0_memory_region>;
};

//&main_r5fss1_core1 {
//	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
//	memory-region = <&main_r5fss1_core1_dma_memory_region>,
//			<&main_r5fss1_core1_memory_region>;
//};

&mcu_m4fss {
	mboxes = <&mailbox0_cluster6 &mbox_m4_0>;
	memory-region = <&mcu_m4fss_dma_memory_region>,
			<&mcu_m4fss_memory_region>; 
};

&main_pmx0 {
	main_mmc1_pins_default: main-mmc1-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x0294, PIN_INPUT, 0) /* (J19) MMC1_CMD */
			AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* (#N/A) MMC1_CLKLB */
			AM64X_IOPAD(0x028c, PIN_INPUT, 0) /* (L20) MMC1_CLK */
			AM64X_IOPAD(0x0288, PIN_INPUT, 0) /* (K21) MMC1_DAT0 */
			AM64X_IOPAD(0x0284, PIN_INPUT, 0) /* (L21) MMC1_DAT1 */
			AM64X_IOPAD(0x0280, PIN_INPUT, 0) /* (K19) MMC1_DAT2 */
			AM64X_IOPAD(0x027c, PIN_INPUT, 0) /* (K18) MMC1_DAT3 */
			AM64X_IOPAD(0x0298, PIN_INPUT, 0) /* (D19) MMC1_SDCD */
		>;
	};

	main_uart0_pins_default: main-uart0-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
			AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
		>;
	};

	main_uart1_pins_default: main-uart1-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
			AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
		>;
	};
	
	main_uart2_pins_default: main-uart2-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x01A8, PIN_INPUT, 10) /* (V1) UART2_RXD  */
			AM64X_IOPAD(0x023c, PIN_OUTPUT, 3) /* (A16) UART2_TXD  UART0_RTSn*/
		>;
	};

	main_uart3_pins_default: main-uart3-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x01AC, PIN_INPUT, 10) /* (W1) UART3_RXD  PRG0_PRU0_GPO19*/
			AM64X_IOPAD(0x024c, PIN_OUTPUT, 4) /* (E16) UART3_TXD  UART1_RTSn*/
		>;
	};
//	icssg0_iep0_pins_default: icssg0-iep0-pins-default {
//		pinctrl-single,pins = <
//			AM64X_IOPAD(0x01AC, PIN_OUTPUT, 2) /* (W1) UART3_RXD  PRG0_PRU0_GPO19*/
//		>;
//	};

//	mdio1_pins_default: mdio1-pins-default {
//		pinctrl-single,pins = <
//			AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
//			AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
//		>;
//	};

	di_do_pins_default: di-do-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x00D0, PIN_INPUT, 7) /* (AA7) PRG1_PRU0_GPO6 GPIO0_51 */
			AM64X_IOPAD(0x00c8, PIN_INPUT, 7) /* (Y8) PRG1_PRU0_GPO4 GPIO0_49 */
			AM64X_IOPAD(0x00C4, PIN_INPUT, 7) /* (V8) PRG1_PRU0_GPO3 GPIO0_48 */
			AM64X_IOPAD(0x00C0, PIN_INPUT, 7) /* (W8) PRG1_PRU0_GPO2 GPIO0_47 */
			AM64X_IOPAD(0x00B8, PIN_OUTPUT, 7) /* (Y7) PRG1_PRU0_GPO0 GPIO0_45 */
			AM64X_IOPAD(0x00BC, PIN_OUTPUT, 7) /* (U8) PRG1_PRU0_GPO1 GPIO0_46 */
			AM64X_IOPAD(0x010c, PIN_OUTPUT, 7) /* (V11) PRG1_PRU1_GPO1 GPIO0_66 */
//			AM64X_IOPAD(0x007c, PIN_OUTPUT, 7) /* (R17) PRG1_PRU1_GPO1 GPIO0_31 */
		>;
	};
	
	net_rst_pin_default:net-rst-pin-default{
		pinctrl-single,pins = <
			AM64X_IOPAD(0x01c4, PIN_OUTPUT, 7) /* (P4) PRG0_PRU1_GPO5 GPIO1_25 */
			AM64X_IOPAD(0x0174, PIN_OUTPUT, 7) /* (R3) PRG0_PRU0_GPO5 GPIO1_5 */
//			AM64X_IOPAD(0x0254, PIN_OUTPUT, 7) /* (B17) GPIO1_61 */
//			AM64X_IOPAD(0x025C, PIN_OUTPUT, 7) /* (D17) GPIO1_63 */
		>;
	};
//	rgmii1_pins_default: rgmii1-pins-default {
//		pinctrl-single,pins = <
//			AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */
//			AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */
//			AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */
//			AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */
//			AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */
//			AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */
//			AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
//			AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
//			AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
//			AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
//			AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
//			AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
//		>;
//	};
//
//       rgmii2_pins_default: rgmii2-pins-default {
//		pinctrl-single,pins = <
//			AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
//			AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
//			AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
//			AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
//			AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
//			AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
//			AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
//			AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
//			AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
//			AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
//			AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
//			AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
//		>;
//	};

	icssg0_mdio0_pins_default: icssg0_mdio_pins_default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x0204, PIN_OUTPUT, 0) /* (P3) PRG0_MDIO0_MDC */
			AM64X_IOPAD(0x0200, PIN_INPUT, 0) /* (P2) PRG0_MDIO0_MDIO */
		>;
	};

	icssg0_rgmii1_pins_default: icssg0-rgmii1-pins-default {                                          
    pinctrl-single,pins = <                                                                   
      AM64X_IOPAD(0x0160, PIN_INPUT, 2) /* (Y1) PRG0_PRU0_GPO0.PRG0_RGMII1_RD0 */       
      AM64X_IOPAD(0x0164, PIN_INPUT, 2) /* (R4) PRG0_PRU0_GPO1.PRG0_RGMII1_RD1 */       
      AM64X_IOPAD(0x0168, PIN_INPUT, 2) /* (U2) PRG0_PRU0_GPO2.PRG0_RGMII1_RD2 */       
      AM64X_IOPAD(0x016c, PIN_INPUT, 2) /* (V2) PRG0_PRU0_GPO3.PRG0_RGMII1_RD3 */       
      AM64X_IOPAD(0x0178, PIN_INPUT, 2) /* (T3) PRG0_PRU0_GPO6.PRG0_RGMII1_RXC */       
      AM64X_IOPAD(0x0170, PIN_INPUT, 2) /* (AA2) PRG0_PRU0_GPO4.PRG0_RGMII1_RX_CTL */   
      AM64X_IOPAD(0x018c, PIN_INPUT, 2) /* (Y3) PRG0_PRU0_GPO11.PRG0_RGMII1_TD0 */      
      AM64X_IOPAD(0x0190, PIN_INPUT, 2) /* (AA3) PRG0_PRU0_GPO12.PRG0_RGMII1_TD1 */     
      AM64X_IOPAD(0x0194, PIN_INPUT, 2) /* (R6) PRG0_PRU0_GPO13.PRG0_RGMII1_TD2 */      
      AM64X_IOPAD(0x0198, PIN_INPUT, 2) /* (V4) PRG0_PRU0_GPO14.PRG0_RGMII1_TD3 */      
      AM64X_IOPAD(0x01a0, PIN_INPUT, 2) /* (U4) PRG0_PRU0_GPO16.PRG0_RGMII1_TXC */      
      AM64X_IOPAD(0x019c, PIN_INPUT, 2) /* (T5) PRG0_PRU0_GPO15.PRG0_RGMII1_TX_CTL */   
	>;                                                                                        
};                                                                                                
                                                                                                  
	icssg0_rgmii2_pins_default: icssg0-rgmii2-pins-default {                                          
    pinctrl-single,pins = <                                                                   
			AM64X_IOPAD(0x01b0, PIN_INPUT, 2) /* (Y2) PRG0_PRU1_GPO0.PRG0_RGMII2_RD0 */       
			AM64X_IOPAD(0x01b4, PIN_INPUT, 2) /* (W2) PRG0_PRU1_GPO1.PRG0_RGMII2_RD1 */       
			AM64X_IOPAD(0x01b8, PIN_INPUT, 2) /* (V3) PRG0_PRU1_GPO2.PRG0_RGMII2_RD2 */       
			AM64X_IOPAD(0x01bc, PIN_INPUT, 2) /* (T4) PRG0_PRU1_GPO3.PRG0_RGMII2_RD3 */       
			AM64X_IOPAD(0x01c8, PIN_INPUT, 2) /* (R5) PRG0_PRU1_GPO6.PRG0_RGMII2_RXC */       
			AM64X_IOPAD(0x01c0, PIN_INPUT, 2) /* (W3) PRG0_PRU1_GPO4.PRG0_RGMII2_RX_CTL */    
			AM64X_IOPAD(0x01dc, PIN_INPUT, 2) /* (W4) PRG0_PRU1_GPO11.PRG0_RGMII2_TD0 */      
			AM64X_IOPAD(0x01e0, PIN_INPUT, 2) /* (Y4) PRG0_PRU1_GPO12.PRG0_RGMII2_TD1 */      
			AM64X_IOPAD(0x01e4, PIN_INPUT, 2) /* (T6) PRG0_PRU1_GPO13.PRG0_RGMII2_TD2 */      
			AM64X_IOPAD(0x01e8, PIN_INPUT, 2) /* (U6) PRG0_PRU1_GPO14.PRG0_RGMII2_TD3 */      
			AM64X_IOPAD(0x01f0, PIN_INPUT, 2) /* (AA4) PRG0_PRU1_GPO16.PRG0_RGMII2_TXC */     
			AM64X_IOPAD(0x01ec, PIN_INPUT, 2) /* (U5) PRG0_PRU1_GPO15.PRG0_RGMII2_TX_CTL */   
  >;                                                                                        
};
                                                                                               

	
	ospi0_pins_default: ospi0-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
			AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
			AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
			AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
			AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
			AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
			AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
			AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
			AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
			AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
			AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
		>;
	};

	main_usb0_pins_default: main-usb0-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
		>;
	};

main_com8_ls_en_pins_default: main-com8-ls-en-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x0254, PIN_OUTPUT, 7) /* (B17) GPIO1_61 */
		>;
	};
	
main_wlan_en_pins_default: main-wlan-en-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x007c, PIN_OUTPUT_PULLUP, 7) /* (R17) GPIO0_31 */
		>;
	};

main_wlan_pins_default: main-wlan-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x00a0, PIN_INPUT, 7) /* (N16) GPIO0_39 */
		>;
	};
//	usr_led_pins_default: usr-led-pins-default {
//		pinctrl-single,pins = <
//			AM64X_IOPAD(0x210, PIN_OUTPUT, 7) /* (D13) PRG1_PRU0_GPO15.GPIO1_44 */
//		>;
//	};
};

&main_gpio0 {
	pinctrl-names = "default";
	pinctrl-0 = <&di_do_pins_default>;
	status = "okay";
};
&main_gpio1 {
	pinctrl-names = "default";
	pinctrl-0 = <&net_rst_pin_default>;
	status = "okay";
};

&main_uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart0_pins_default>;
};

/* main_uart1 is reserved for firmware usage */
&main_uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart1_pins_default>;
};

&main_uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart2_pins_default>;
};

&main_uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart3_pins_default>;
};

&main_uart4 {
	status = "disabled";
};

&main_uart5 {
status = "disabled";
};

&main_uart6 {
		status = "disabled";
};

&mcu_uart0 {
	status = "disabled";
};

&mcu_uart1 {
	status = "disabled";
};

&main_i2c1 {
	status = "disabled";
};

/* mcu_gpio0 is reserved for mcu firmware usage */
&mcu_gpio0 {
	status = "reserved";
};

&mcu_i2c0 {
	status = "disabled";
};

&main_i2c0 {
	status = "disabled";
};

&main_i2c2 {
	status = "disabled";
};

&main_i2c3 {
	status = "disabled";
};

&mcu_i2c1 {
	status = "disabled";
};

&mcu_spi0 {
	status = "disabled";
};

&mcu_spi1 {
	status = "disabled";
};

&main_spi0 {
	status = "disabled";
};

&sdhci0 {
	/* emmc */
	bus-width = <8>;
	non-removable;
	ti,driver-strength-ohm = <50>;
	disable-wp;
};

&sdhci1 {
	status = "okay";
//	vmmc-supply = <&wlan_en>;
//	pinctrl-names = "default";
//	pinctrl-0 = <&main_mmc1_pins_default>;
//	bus-width = <4>;
//	non-removable;
//	cap-power-off-card;
//	keep-power-in-suspend;
//	ti,driver-strength-ohm = <50>;
//
//	#address-cells = <1>;
//	#size-cells = <0>;
//	wlcore: wlcore@2 {
//		compatible = "ti,wl1837";
//		reg = <2>;
//		pinctrl-0 = <&main_wlan_pins_default>;
//		pinctrl-names = "default";
//		interrupt-parent = <&main_gpio0>;
//		interrupts = <39 IRQ_TYPE_EDGE_FALLING>; 
//	};
	/* SD/MMC */ 
	pinctrl-names = "default";
	bus-width = <4>;
	pinctrl-0 = <&main_mmc1_pins_default>;
	ti,driver-strength-ohm = <50>;
	disable-wp;  
	no-1-8-v;    
};


&usbss0 {
	ti,vbus-divider;
	ti,usb2-only;
};

&usb0 {
	dr_mode = "host";//"otg";
	maximum-speed = "high-speed";
	pinctrl-names = "default"; 
	pinctrl-0 = <&main_usb0_pins_default>;
};

&cpsw3g {
	status = "disabled";
//	pinctrl-names = "default";
//	pinctrl-0 = <&mdio1_pins_default
//		     &rgmii1_pins_default
//		     &rgmii2_pins_default>;
////		cpts@3d000 {
////		ti,pps = <7 1>;
////	};
};

//&cpsw_port1 {
//	phy-mode = "rgmii-rxid";
//	phy-handle = <&cpsw3g_phy0>;
//};
//
//&cpsw_port2 {
//	phy-mode = "rgmii-rxid";
//	phy-handle = <&cpsw3g_phy1>;
//};

&cpsw3g_mdio {
	status = "disabled";
//	cpsw3g_phy0: ethernet-phy@1 {
//		reg = <1>;
//		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
//		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
//	};
//
//	cpsw3g_phy1: ethernet-phy@0 {
//		reg = <0>;
//		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
//		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
//	};
};

//#define TS_OFFSET(pa, val)     (0x4+(pa)*4) (0x10000 | val)
//
//&timesync_router {
//	pinctrl-names = "default";
//	pinctrl-0 = <&mcu_cpts_pps>;
//
//	/* Example of the timesync routing */
//	mcu_cpts_pps: mcu-cpts-pps {
//		pinctrl-single,pins = <
//				/* pps [cpts genf1] in22 -> out37 [cpts hw8_push] */
//				TS_OFFSET(37, 22)
//				/* pps [cpts genf1] in22 -> out25 [SYNC1_OUT pin] */
//				TS_OFFSET(25, 22)
//				>;
//	};
//};

/* set R5F subsystem 0 to single-CPU mode */
&main_r5fss0 {
	ti,cluster-mode = <2>;
};
&main_r5fss1 {
	ti,cluster-mode = <2>; 
};

&mailbox0_cluster2 {
	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
		ti,mbox-rx = <0 0 2>;
		ti,mbox-tx = <1 0 2>;
	};

//	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
//		ti,mbox-rx = <2 0 2>;
//		ti,mbox-tx = <3 0 2>;
//	};
};

&mailbox0_cluster3 {
	status = "disabled";
};

&mailbox0_cluster4 {
	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
		ti,mbox-rx = <0 0 2>;
		ti,mbox-tx = <1 0 2>;
	};

//	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
//		ti,mbox-rx = <2 0 2>;
//		ti,mbox-tx = <3 0 2>;
//	};
};

&mailbox0_cluster5 {
	status = "disabled";
};

&mailbox0_cluster6 {
	mbox_m4_0: mbox-m4-0 {
		ti,mbox-rx = <0 0 2>;
		ti,mbox-tx = <1 0 2>;
	};
};

&mailbox0_cluster7 {
	status = "disabled";
};

&serdes_ln_ctrl {
	idle-states = <AM64_SERDES0_LANE0_PCIE0>;
};

&serdes0 {
	serdes0_pcie_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
		resets = <&serdes_wiz0 1>;
	};
};

&pcie0_rc {
	status = "disabled";
};

&pcie0_ep {
	status = "disabled";
};

&tscadc0 {
	/* ADC is reserved for R5 usage */
	status = "reserved";
};

&ospi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&ospi0_pins_default>;

	flash@0{
		compatible = "jedec,spi-nor";
		reg = <0x0>;
		spi-tx-bus-width = <8>;
		spi-rx-bus-width = <8>;
		spi-max-frequency = <25000000>;
		cdns,tshsl-ns = <60>;
		cdns,tsd2d-ns = <60>;
		cdns,tchsh-ns = <60>;
		cdns,tslch-ns = <60>;
		cdns,read-delay = <4>;
		cdns,phy-mode;
		#address-cells = <1>;
		#size-cells = <1>;
	};
};

&main_mcan0 {
	status = "disabled";
};

&main_mcan1 {
	status = "disabled";

};

&icssg0_mdio {
        pinctrl-names = "default";
        pinctrl-0 = <&icssg0_mdio0_pins_default>;
        reset-gpios = <&main_gpio1 25 GPIO_ACTIVE_LOW>,<&main_gpio1 5 GPIO_ACTIVE_LOW>;
        reset-delay-us = <2>; /* PHY datasheet states 1uS min */
        reset-post-delay-us = <2>;
        status = "okay";

        icssg0_phy1: ethernet-phy@0 {
                reg = <0>;
//                ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
                ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
                ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
        };

        icssg0_phy2: ethernet-phy@1 {
                reg = <1>;
//                ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
                ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
                ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
        
				};
};

/*&icssg0_iep0 {
	status = "okay";
//	pinctrl-names = "default";
//	pinctrl-0 = <&icssg0_iep0_pins_default>;
};*/
   
&icssg1_mdio {
	status = "disabled";
};
&gpmc0 {
	status = "disabled";
};

Hello，

    The issue I raised hasn't been resolved yet. Are there any new findings based on the code I provided? Additionally, I've discovered another problem.

    When using a GPIO as an external interrupt, the R5F core alone can correctly detect and handle the interrupt. However, after the linux core boots the R5F core , debugging via CCS shows that the GPIO_getBankIntrStatus function returns a status value of 0 when entering the interrupt service routine (ISR). Since this value does not match the defined GPIO pin’s expected status, the interrupt handler is not executed.Why does the external interrupt in the R5F core fail to be recognized after the linux core boots the R5F core?What is the root cause of the GPIO_getBankIntrStatus returning 0 in this scenario?I  share my code.

void FPGA_INT_Init(void) {
    HwiP_Params     hwiPrms1;
    int32_t         retVal=0;
    uint32_t        intrNum3,bankNum3;

    intrNum3 = Board_getGpioButtonIntrNum();
    bankNum3 = GPIO_GET_BANK_INDEX(FPGAInt_CPLD);
    Board_gpioInit(FPGAInt_CPLD);
    /*Setup GPIO for interrupt generation*/
    GPIO_setDirMode(FPGAInt_CPLD_CSL, FPGAInt_CPLD, GPIO_DIRECTION_INPUT);
    GPIO_setTrigType(FPGAInt_CPLD_CSL, FPGAInt_CPLD, GPIO_TRIG_TYPE_FALL_EDGE);//下降沿触发
    GPIO_bankIntrEnable(FPGAInt_CPLD_CSL, bankNum3);

    /*Register pin interrupt*/
    HwiP_Params_init(&hwiPrms1);
    hwiPrms1.intNum   = intrNum3;
    hwiPrms1.callback = FPGA_INTFxn;
    hwiPrms1.args     = (void *) (FPGAInt_CPLD);
    hwiPrms1.isFIQ = 0;
    hwiPrms1.isPulse = 1;
    //GPIO interrupt is a pulse type interrupt
    hwiPrms1.priority = 0;//
    retVal = HwiP_construct(&gGpioHwiObject1, &hwiPrms1);
    DebugP_assert(retVal == SystemP_SUCCESS );
}
static void Sciclient_gpioIrqSet(uint32_t pinNum)
{
    int32_t                             retVal;
    struct tisci_msg_rm_irq_set_req     rmIrqReq;
    struct tisci_msg_rm_irq_set_resp    rmIrqResp;
    rmIrqReq.valid_params           = 0U;
    rmIrqReq.valid_params          |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
    rmIrqReq.valid_params          |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
    rmIrqReq.global_event           = 0U;
    rmIrqReq.src_id                 = TISCI_DEV_GPIO0;
    rmIrqReq.src_index              = TISCI_BANK_SRC_IDX_BASE_GPIO0 + GPIO_GET_BANK_INDEX(pinNum);
    rmIrqReq.dst_id                 = TISCI_DEV_R5FSS0_CORE0;
    rmIrqReq.dst_host_irq           = CSLR_R5FSS0_CORE0_INTR_MAIN_GPIOMUX_INTROUTER0_OUTP_2;
    rmIrqReq.ia_id                  = 0U;
    rmIrqReq.vint                   = 0U;
    rmIrqReq.vint_status_bit_index  = 0U;
    rmIrqReq.secondary_host         = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;

    retVal = Sciclient_rmIrqSet(&rmIrqReq, &rmIrqResp, SystemP_WAIT_FOREVER);
}
void FPGA_INTFxn(void *args) {//FPGA中断读取数据
    uint32_t    pinNum = (uint32_t) args;
    uint32_t    bankNum1 =  GPIO_GET_BANK_INDEX(pinNum);
    uint32_t    intrStatus;
    uint32_t    pinMask1 = GPIO_GET_BANK_BIT_MASK(pinNum);

    /* Get and clear bank interrupt status */
    intrStatus = GPIO_getBankIntrStatus(FPGAInt_CPLD_CSL, bankNum1);
    GPIO_clearBankIntrStatus(FPGAInt_CPLD_CSL, bankNum1, intrStatus);

    /* Per pin interrupt handling */
    if((intrStatus&pinMask1))
    {
        Localbus();
    }
    else
        fpgaintcnt++;
}

Hello，

     Is there anything news？We urgently need to understand the reasons behind this issue, as it is currently impeding our progress. We would greatly appreciate any suggestions you could provide.

Hello，

     Is there anything news？We urgently need to understand the reasons behind this issue, as it is currently impeding our progress. We would greatly appreciate any suggestions you could provide.

Hello Wanglili,

In the working case (R5F initialized on its own without Linux), how are you initializing the processor? Are you using SPL boot, or SBL boot? I assume you are using SPL boot with the Linux initialization method.

Regards,

Nick

Actually, before we get into boot flows: are you making sure to disable the GPIO bank interrupt in Linux? See the note at

https://software-dl.ti.com/mcu-plus-sdk/esd/AM64X/10_01_00_32/exports/docs/api_guide_am64x/EXAMPLES_DRIVERS_GPIO_INPUT_INTERRUPT.html

Regards,

Nick

Hello，

    Thanks for answeing me.I have defined several input/output pins as well as an Ethernet reset pin in the device tree. Currently, if I define main_gpio_intr as "reserve", the Linux system halts during the detection of the Ethernet reset pin, resulting in an unsuccessful system boot. However, in my understanding, even though I am using these pins, I am not utilizing their interrupt functionality, so this issue should not occur. The current situation is that the real-time kernel can recognize interrupts, but after an interrupt is detected and the function intrStatus = GPIO_getBankIntrStatus(gGpioBaseAddr, bankNum); is called, the returned value is 0, indicating that it's not the pin I defined. Could this be an issue related to the interrupt configuration in the device tree?

Hello Wanglili,

Apologies for pointing you in several different directions here. I am realizing that the example note may be incorrect, or at least not contain all the needed information.

Please refer to this FAQ:
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1198105/faq-am64x-how-to-run-mcu-sdk-gpio_input_interrupt-example-for-r5fss0-0-with-linux-running-on-a53

Are you using SBL boot or SPL boot? And remind me which SDK version this is?

Regards,

Nick

Hello，

We use  SPL boot,SDK version is 8.6.

Hello Wanglili,

Please try using the k3 resource partition tool to make the interrupt updates that are suggested in the GPIO FAQ I linked above.

You can find an FAQ about using the k3 resource partition tool with Linux SDK 8.6 here:
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1230630/faq-how-to-get-started-with-resource-partitioning-tool

Regards,

Nick

Hello，

    After we switch from the non-real-time kernel to the real-time kernel currently, we are able to detect GPIO interrupts in the real-time kernel. However, there are instances where, upon entering the interrupt service routine (ISR), the return value of the GPIO_getBankIntrStatus function is 0. If we follow the solution you provided, does it address scenarios where there are absolutely no interrupts occurring, or is it meant to resolve a different issue?

Hello，

    After we switch from the non-real-time kernel to the real-time kernel currently, we are able to detect GPIO interrupts in the real-time kernel. However, there are instances where, upon entering the interrupt service routine (ISR), the return value of the GPIO_getBankIntrStatus function is 0. If we follow the solution you provided, does it address scenarios where there are absolutely no interrupts occurring, or is it meant to resolve a different issue?

Hello Wanglili,

I have not run tests myself at this point in time. However, I would expect that if the interrupt router is not configured to send interrupts to a core, then that core would not receive any interrupts at all from the GPIO.

Regards,

Nick

Hello，

    The return value of GPIO_getBankIntrStatus I mentioned being 0 is not always zero. It intermittently returns 0 during normal responses—sometimes the interrupt entry value is correct, while other times it reads 0. Could this phenomenon be caused by a non-real-time core configuring an interrupt somewhere, processing it before the real-time core, and then clearing the corresponding pin's interrupt status? This is my hypothesis, as I did not use interrupt pins or configure any interrupt-related settings in the actual device tree configuration.

Hello Wanglili,

Heads up, I will be on vacation for the next week. I will be back in the office in June. I did not get the chance to dig more into exactly how these interrupts work (my expectation would be that an interrupt cannot be routed to multiple cores at the same time, but I am not sure). Feel free to ping the thread on Thursday or Friday of the first week of June if we need to continue the discussion.

Regards,

Nick

Hello，

    OK,I will waiting your message。Thank you ！