Tool/software:
Hello TI Support,
I'm working on the AM64x platform and trying to enable CPU frequency scaling on the Cortex-A53 cores. I’ve enabled required kernel options and modified the device tree to include a valid OPP table and added opp-table with the reference opp-table given in the processor sdk of Am62x(ref: https://software-dl.ti.com/processor-sdk-linux/esd/AM62X/latest/exports/docs/linux/Foundational_Components/Power_Management/pm_dfs.html)
And currently i am using AM64x processor SDK version: 10.01.10.04
But I am unable to see the scaling options in /sys/devices/system/cpu/cpufreq.
Changes done in menuconfig:
CONFIG_CPU_IDLE=y
CONFIG_ARM_PSCI_CPUIDLE=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=m
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
CONFIG_CPUFREQ_DT=m
CONFIG_ARM_SCMI_CPUFREQ=y
CONFIG_VIRTUALIZATION=y
CONFIG_JUMP_LABEL=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_BLK_DEV_INTEGRITY=y
My current k3-am642.dtsi with OPP-table.
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for AM642 SoC family in Dual core configuration
*
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include "k3-am64.dtsi"
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0: cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
};
};
cpu0: cpu@0 {
compatible = "arm,cortex-a53";
reg = <0x000>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&L2_0>;
operating-points-v2 = <&a53_opp_table>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53";
reg = <0x001>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&L2_0>;
operating-points-v2 = <&a53_opp_table>;
};
};
a53_opp_table: opp-table {
compatible = "operating-points-v2-ti-cpu";
opp-shared;
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
};
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
};
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
};
};
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x40000>;
cache-line-size = <64>;
cache-sets = <256>;
};
};
