C6678 DDR3 Controller Problem

Adam,

Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages. Be sure to search those for helpful information and to browse for questions others may have asked on similar topics.

You have gathered a lot of information that is helpful for us to understand your situation. It definitely sounds like the initialization process is shutting down the DDR peripheral in some way, particularly from your observation of the DDRCLKOUT0 P/N signals. My suggestion is to step through the initialization commands to find the one that makes the clock outputs go away. An easy way would be to do this in a GEL file, but you can also do it through CCS in your code, keeping in mind there may be pipeline delays from the instruction indicated in CCS to the actual write to the peripheral - compile this in Debug for stepping and/or add a small delay loop after writes.

Regards,
RandyP

If you need more help, please reply back. If this answers the question, please click  Verify Answer  , below.

RandyP,

Thanks for the quick reply. The instruction that kills the clock seems to be the one that initiates full read-write leveling by setting bit 31 of  the RDWR_LVL_CTRL register to 1 as we step through the code. I can then get the clock to reappear by toggling PHY_RST in the DDR_PHY_CTRL_1 register. However, even when just trying to run it without using the full leveling feature, I still seem to get the symptom of the controller not driving anything to the bus. For example, the DDR_RESET line never exceeding 0.75V. The RESET line may be a separate issue though as I noticed that the EVM board does not really do a great job controlling that line either. It seems to only drive it up to 1.0V, but at least it is trying.

Adam

Adam,

We have observed that most issues are traced back to DDR configuration or routing. We can start by verifying the configuration sequence. Can you provide the following information?

- DDR configuration sequence from the GEL that you have

- The trace lengths for each DQS (average of P and N) and CK pair (also average of P and N). As a sanity check for us to verify the values you have in the config sequence.

Regards,

Aditya

Here are the trace lengths from layout in mils:

Byte lanes 0 and 1:

CLK: 2851.18 (N: 2849.53, P: 2852.83)

DQS0: 1552.78 (N:1553.19, P: 1552.37)

DQS1: 1553.30 (N:1553.22, P: 1553.37)

Byte lanes 2 and 3:

CLK: 2227.22 (N: 2225.63, P: 2228.2)

DQS2: 1553.05 (N:1552.66, P: 1553.44)

DQS3: 1553.24 (N:1553.76, P: 1552.71)

And the gel configuration sequence:

/*--------------------------------------------------------------*/
/* ddr3_setup()                                                  */
/* DDR3 initialization                                          */
/*--------------------------------------------------------------*/
int flag;
ddr3_setup_auto_lvl_1333()
{
    int i,TEMP,startlo, stoplo,starthi, stophi;
    KICK0 = KICK0_UNLOCK;
    KICK1 = KICK1_UNLOCK;
   
  
  /***************** 2.2 DDR3 PLL Configuration ************/
    DDR3PLLCTL1 |= 0x00000040;      //Set ENSAT bit = 1 50-70ms
    DDR3PLLCTL1 |= 0x00002000;      //Set RESET bit = 1 50-70ms
    DDR3PLLCTL0 = 0x090804C0;       //Configure CLKR, CLKF, CLKOD, BWADJ ~60ms
 //Wait for 5us min. Actual delay in GEL here is in tens of ms
    DDR3PLLCTL1 &= ~(0x00002000);   //Clear RESET bit
    //Wait for PLL to lock = min 500 ref clock cycles. With refclk = 100MHz, = 5000 ns = 5us. Actualy delay between 2 GEL steps = ~6ms

  /**************** 3.0 Leveling Register Configuration ********************/
  /* Using partial automatic leveling due to errata */
 
  /**************** 3.2 Invert Clock Out ********************/
    DDR3_CONFIG_REG_0 &= ~(0x007FE000);  // clear ctrl_slave_ratio field
    DDR3_CONFIG_REG_0 |= 0x00200000;     // set ctrl_slave_ratio to 0x100
    DDR3_CONFIG_REG_12 |= 0x08000000;    // Set invert_clkout = 1
    DDR3_CONFIG_REG_0 |= 0xF;            // set dll_lock_diff to 15
    DDR3_CONFIG_REG_23 |= 0x00000200;    //Set bit 9 = 1 to use forced ratio leveling for read DQS
    //Values with invertclkout = 1
  /**************** 3.3+3.4 Partial Automatic Leveling ********************/
  DATA0_WRLVL_INIT_RATIO = 0x00;
  DATA1_WRLVL_INIT_RATIO = 0x00;
  DATA2_WRLVL_INIT_RATIO = 0x00;
  DATA3_WRLVL_INIT_RATIO = 0x00;
  DATA4_WRLVL_INIT_RATIO = 0x12;
  DATA5_WRLVL_INIT_RATIO = 0x12;
  DATA6_WRLVL_INIT_RATIO = 0x24;
  DATA7_WRLVL_INIT_RATIO = 0x24;
  DATA8_WRLVL_INIT_RATIO = 0x00;

  DATA0_GTLVL_INIT_RATIO = 0x00;
  DATA1_GTLVL_INIT_RATIO = 0x00;
  DATA2_GTLVL_INIT_RATIO = 0x00;
  DATA3_GTLVL_INIT_RATIO = 0x00;
  DATA4_GTLVL_INIT_RATIO = 0x9C;
  DATA5_GTLVL_INIT_RATIO = 0x9C;
  DATA6_GTLVL_INIT_RATIO = 0xAE;
  DATA7_GTLVL_INIT_RATIO = 0xAE;
  DATA8_GTLVL_INIT_RATIO = 0x00;
 
  //Do a PHY reset. Toggle DDR_PHY_CTRL_1 bit 15 0->1->0
  DDR_DDRPHYC &= ~(0x00008000);
  DDR_DDRPHYC |= (0x00008000);
  DDR_DDRPHYC &= ~(0x00008000);

  /***************** 2.3 Basic Controller and DRAM configuration ************/
  DDR_SDRFC    = 0x00005162;    // enable configuration

  /* DDR_SDTIM1   = 0x1113783C; */
   TEMP = 0;
   TEMP |= 0x8 << 25; // T_RP bit field 28:25
   TEMP |= 0x8 << 21; // T_RCD bit field 24:21
   TEMP |= 0x9 << 17; // T_WR bit field 20:17
   TEMP |= 0x17 << 12; // T_RAS bit field 16:12
   TEMP |= 0x20 << 6; // T_RC bit field 11:6
   TEMP |= 0x7 << 3; // T_RRD bit field 5:3
   TEMP |= 0x4; // T_WTR bit field 2:0
   DDR_SDTIM1 = TEMP;

  /* DDR_SDTIM2   = 0x304F7FE3; */
   TEMP = 0;
   TEMP |= 0x3 << 28; // T_XP bit field 30:28
   TEMP |= 0x71 << 16; // T_XSNR bit field 24:16
   TEMP |= 0x1ff << 6; // T_XSRD bit field 15:6
   TEMP |= 0x4 << 3; // T_RTP bit field 5:3
   TEMP |= 0x3; // T_CKE bit field 2:0
   DDR_SDTIM2 = TEMP;

  /*  DDR_SDTIM3   = 0x559F849F; */
   TEMP = 0;
   TEMP |= 0x5 << 28; // T_PDLL_UL bit field 31:28 (fixed value)
   TEMP |= 0x5 << 24; // T_CSTA bit field 27:24 (fixed value)
   TEMP |= 0x4 << 21; // T_CKESR bit field 23:21
   TEMP |= 0x3f << 15; // T_ZQCS bit field 20:15
   TEMP |= 0x6A << 4; // T_RFC bit field 12:4
   TEMP |= 0xf; // T_RAS_MAX bit field 3:0 (fixed value)
   DDR_SDTIM3 = TEMP;

    DDR_DDRPHYC  = 0x0010010F;
   
    DDR_ZQCFG    = 0x70073214;

    DDR_PMCTL    = 0x0;
   
    DDR_SDRFC = 0x00005162; // enable configuration

    /* DDR_SDCFG    = 0x63062A32; */
    /* New value with DYN_ODT disabled and SDRAM_DRIVE = RZQ/7 //0x63222A32;    // last config write DRAM init occurs */
     TEMP = 0;
     TEMP |= 0x3 << 29; // SDRAM_TYPE bit field 31:29 (fixed value)
     TEMP |= 0x0 << 27; // IBANK_POS bit field 28:27
     TEMP |= 0x3 << 24; // DDR_TERM bit field 26:24
     TEMP |= 0x0 << 21; // DYN_ODT bit field 22:21
     TEMP |= 0x1 << 18; // SDRAM_DRIVE bit field 19:18
     TEMP |= 0x2 << 16; // CWL bit field 17:16
     TEMP |= 0x1 << 14; // NM bit field 15:14
     TEMP |= 0xA << 10; // CL bit field 13:10
     TEMP |= 0x5 << 7; // ROWSIZE bit field 9:7
     TEMP |= 0x3 << 4; // IBANK bit field 6:4
     TEMP |= 0x0 << 3; // EBANK bit field 3:3
     TEMP |= 0x3; // PAGESIZE bit field 2:0
     DDR_SDCFG = TEMP;
         

    //Wait 600us for HW init to complete
    DDR_SDRFC = 0x00001450;       //Refresh rate = (7.8*666MHz]

    RDWR_LVL_RMP_CTRL = 0x80000000; //enable full leveling
  
    RDWR_LVL_CTRL = 0x80000000; //Trigger full leveling - This ignores read DQS leveling result and uses ratio forced value              //(0x34) instead
    //Wait for min 1048576 DDR clock cycles for leveling to complete = 1048576 * 1.5ns = 1572864ns = 1.57ms.
    //Actual time = ~10-15 ms

    GEL_TextOut("\nDDR3 initialization is complete.\n");
}

Thanks,

Adam

Adam,

Sorry for the delay. I don't know if you root caused this issue.

Based on your trace lengths and assuming a refclk = 66.67 MHz (DDR clock = 666.67MHz) the *_WR_LVL_INIT_RATIOs give me:

The *_GT_LVL_INIT_RATIOs give me:

These are pretty close to what you have so it shouldn't matter. To verify your configuration, I will need the DRAM part number that you have populated on your board.