Tool/software:
HI Expert,
My customer tested there is difference between warm reset and cold reset as below:
1. The time from cold reset to "read" is 436us
2. The time from warm reset to "read" is 51us, and it's failed
MPU from 32MB SPI NOR Flash loader, using Jinghao 2Gbit DDR3L, exclude NOR Flash 3/4 byte switching causes boot failure.
Compare with the warm and cold reset, SPI read and write signal and DDR reset, CKE, ODT signal, differences in the initialization timing were found, as detailed in the waveform and illustrated information. Jinghao confirmed it required T ≥ 500us otherwise it cannot start.
The questions are:
1. How to adjust the CKE time T after reset?
2. They found the describe in datasheet: "The user must tie off the config_refresh_def_val port with a correct value to meet the typical DDR3 device specified delay time of 500 us between the deassertion of reset and the assertion of CKE" , but they don't find the information of how-to config "config_refresh_def_val", could you help confirm where to set up?
BR,
Moon
