AM6442: Set CPSW up in no_phy mode

Robert Morse

Part Number: AM6442
Other Parts Discussed in Thread: SYSCONFIG,

Tool/software:

Hi,

Is there an example of how to set up the CPSW in no_phy mode. I have a situation where have the CPSW connected to another device (Anybus-M40 in RMII mode),

The device is fixed at 100Mbps Full duplex.

After selecting no_phy mode, sysConfig does not give me the ability to force the Speed & Duplex.

Then when trying to compile, I get the following un-defines:

EnetApp_isPortLinked   obj/debug/ti_enet_lwipif.obj
EnetBoard_getId        obj/debug/ti_enet_open_close.obj
EnetBoard_getMiiConfig obj/debug/ti_enet_open_close.obj
EnetBoard_getPhyCfg    obj/debug/ti_enet_open_close.obj
EnetBoard_setupPorts   obj/debug/ti_enet_open_close.obj
gEnetPhyDrvTbl         c:/ti/mcu_plus_sdk_am64x_10_01_00_32/source/networking/enet/lib/enet-cpsw.am64x.r5f.ti-arm-clang.debug.lib<enetphy.obj>

I understand the EnetApp_isPortLinked function, as that can be used to bring the port up or down to the stack.

But the others, as I do not have a phy, not sure how to use them.

Any Help would be great.

Robert

5 months ago

0 Ashwani Goel 5 months ago

TI__Mastermind 27320 points

Hi Robert,

Thanks for your query.

Robert Morse said:
Is there an example of how to set up the CPSW in no_phy mode.

Hopefully below documentation will be helpful

AM243x MCU+ SDK: MAC2MAC support

Let me know if you need further help.

Regards

Ashwani

0 Robert Morse 5 months ago in reply to Ashwani Goel

Prodigy 180 points

That was one of the ways I tried, but still get the following as undefined:

undefined first referenced
symbol in file
--------- ----------------
EnetBoard_getId obj/debug/ti_enet_open_close.obj
EnetBoard_getMiiConfig obj/debug/ti_enet_open_close.obj
EnetBoard_getPhyCfg obj/debug/ti_enet_open_close.obj
EnetBoard_setupPorts obj/debug/ti_enet_open_close.obj
gEnetPhyDrvTbl c:/ti/mcu_plus_sdk_am64x_10_01_00_32/source/networking/enet/lib/enet-cpsw.am64x.r5f.ti-arm-clang.debug.lib<enetphy.obj>

The ti_enet_open_close.c still has all the calls for the PHY config.

Robert

Here is the syscfg file for the CPU that is controlling the port.

======================================================================================================================

/**
* These arguments were used when this file was generated. They will be automatically applied on subsequent loads
* via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
* @cliArgs --device "AM64x" --part "Default" --package "ALV" --context "r5fss1-1" --product "MCU_PLUS_SDK_AM64x@10.01.00"
* @v2CliArgs --device "AM6442" --package "FCBGA (ALV)" --variant "AM6442-D" --context "r5fss1-1" --product "MCU_PLUS_SDK_AM64x@10.01.00"
* @versions {"tool":"1.21.2+3837"}
*/

/**
* Import the modules used in this configuration.
*/
const eeprom = scripting.addModule("/board/eeprom/eeprom", {}, false);
const eeprom1 = eeprom.addInstance();
const ethphy_cpsw_icssg = scripting.addModule("/board/ethphy_cpsw_icssg/ethphy_cpsw_icssg", {}, false);
const ethphy_cpsw_icssg1 = ethphy_cpsw_icssg.addInstance();
const gpio = scripting.addModule("/drivers/gpio/gpio", {}, false);
const gpio1 = gpio.addInstance();
const gpio2 = gpio.addInstance();
const gpio3 = gpio.addInstance();
const gpio4 = gpio.addInstance();
const gtc = scripting.addModule("/drivers/gtc/gtc");
const i2c = scripting.addModule("/drivers/i2c/i2c", {}, false);
const i2c1 = i2c.addInstance();
const ipc = scripting.addModule("/drivers/ipc/ipc");
const mcspi = scripting.addModule("/drivers/mcspi/mcspi", {}, false);
const mcspi1 = mcspi.addInstance();
const debug_log = scripting.addModule("/kernel/dpl/debug_log");
const dpl_cfg = scripting.addModule("/kernel/dpl/dpl_cfg");
const mpu_armv7 = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false);
const mpu_armv71 = mpu_armv7.addInstance();
const mpu_armv72 = mpu_armv7.addInstance();
const mpu_armv73 = mpu_armv7.addInstance();
const mpu_armv74 = mpu_armv7.addInstance();
const mpu_armv75 = mpu_armv7.addInstance();
const mpu_armv76 = mpu_armv7.addInstance();
const mpu_armv77 = mpu_armv7.addInstance();
const mpu_armv78 = mpu_armv7.addInstance();
const mpu_armv79 = mpu_armv7.addInstance();
const default_linker = scripting.addModule("/memory_configurator/default_linker", {}, false);
const default_linker1 = default_linker.addInstance();
const general = scripting.addModule("/memory_configurator/general", {}, false);
const general1 = general.addInstance();
const region = scripting.addModule("/memory_configurator/region", {}, false);
const region1 = region.addInstance();
const section = scripting.addModule("/memory_configurator/section", {}, false);
const section1 = section.addInstance();
const section2 = section.addInstance();
const section3 = section.addInstance();
const section4 = section.addInstance();
const section5 = section.addInstance();
const section6 = section.addInstance();
const section7 = section.addInstance();
const section8 = section.addInstance();
const section9 = section.addInstance();
const section10 = section.addInstance();
const section11 = section.addInstance();
const section12 = section.addInstance();
const section13 = section.addInstance();
const section14 = section.addInstance();
const section15 = section.addInstance();
const section16 = section.addInstance();
const enet_cpsw = scripting.addModule("/networking/enet_cpsw/enet_cpsw", {}, false);
const enet_cpsw1 = enet_cpsw.addInstance();

/**
* Write custom configuration values to the imported modules.
*/
eeprom1.$name = "CONFIG_EEPROM0";

gpio1.$name = "CONFIG_GPIO_ANYBUS_M0";
gpio1.GPIO.gpioPin.pu_pd = "pu";
gpio1.GPIO.gpioPin.$assign = "PRG0_PRU0_GPO11";

gpio2.$name = "CONFIG_GPIO_ANYBUS_M1";
gpio2.GPIO.gpioPin.pu_pd = "pu";
gpio2.GPIO.gpioPin.$assign = "PRG0_PRU0_GPO12";

gpio3.pinDir = "OUTPUT";
gpio3.defaultValue = "1";
gpio3.$name = "CONFIG_GPIO_ANYBUS_RESET";
gpio3.GPIO.gpioPin.$assign = "PRG0_PRU0_GPO6";

gpio4.enableIntr = true;
gpio4.trigType = "FALL_EDGE";
gpio4.$name = "CONFIG_GPIO_ANYBUS_INTn";
gpio4.GPIO.gpioPin.pu_pd = "pu";
gpio4.GPIO.gpioPin.$assign = "PRG0_PRU0_GPO7";

i2c1.$name = "CONFIG_I2C1";
eeprom1.peripheralDriver = i2c1;
i2c1.I2C_child.$name = "drivers_i2c_v0_i2c_v0_template0";

ipc.a53ss0_0 = "notify_rpmsg";
ipc.m4fss0_0 = "NONE";

mcspi1.$name = "CONFIG_MCSPI0";
mcspi1.sdkInfra = "LLD";
mcspi1.intrEnable = "POLLED";
mcspi1.SPI.CLK.$assign = "SPI0_CLK";
mcspi1.SPI.D0.$assign = "SPI0_D0";
mcspi1.SPI.D1.$assign = "SPI0_D1";
mcspi1.mcspiChannel[0].$name = "CONFIG_MCSPI_CH0";
mcspi1.mcspiChannel[0].CSn.$assign = "SPI0_CS0";
mcspi1.child.$name = "drivers_mcspi_v0_mcspi_v0_template_lld0";

debug_log.enableCssLog = false;
debug_log.enableLogZoneInfo = true;
debug_log.enableMemLog = true;
debug_log.enableUartLog = true;
debug_log.uartLog.$name = "CONFIG_UART0";

const uart_v0_template = scripting.addModule("/drivers/uart/v0/uart_v0_template", {}, false);
const uart_v0_template1 = uart_v0_template.addInstance({}, false);
uart_v0_template1.$name = "drivers_uart_v0_uart_v0_template0";
debug_log.uartLog.child = uart_v0_template1;

mpu_armv71.$name = "CONFIG_MPU_REGION0";
mpu_armv71.size = 31;
mpu_armv71.attributes = "Device";
mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD";
mpu_armv71.allowExecute = false;

mpu_armv72.$name = "CONFIG_MPU_REGION1";
mpu_armv72.size = 15;
mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD";

mpu_armv73.$name = "CONFIG_MPU_REGION2";
mpu_armv73.baseAddr = 0x41010000;
mpu_armv73.size = 15;
mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD";

mpu_armv74.$name = "CONFIG_MPU_REGION3";
mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD";
mpu_armv74.baseAddr = 0x70000000;
mpu_armv74.size = 21;

mpu_armv75.$name = "CONFIG_MPU_REGION4";
mpu_armv75.baseAddr = 0x701D0000;
mpu_armv75.size = 16;
mpu_armv75.attributes = "NonCached";
mpu_armv75.allowExecute = false;

mpu_armv76.$name = "CONFIG_MPU_REGION5";
mpu_armv76.baseAddr = 0x60000000;
mpu_armv76.size = 28;
mpu_armv76.accessPermissions = "Supervisor RD, User RD";

mpu_armv77.$name = "CONFIG_MPU_REGION6";
mpu_armv77.baseAddr = 0xE0000000;
mpu_armv77.size = 28;

mpu_armv78.$name = "CONFIG_MPU_REGION7";
mpu_armv78.baseAddr = 0xF0000000;
mpu_armv78.attributes = "NonCached";
mpu_armv78.allowExecute = false;
mpu_armv78.size = 28;

mpu_armv79.$name = "CONFIG_MPU_REGION8";
mpu_armv79.baseAddr = 0x50000000;
mpu_armv79.attributes = "NonCached";
mpu_armv79.allowExecute = false;
mpu_armv79.size = 27;

default_linker1.$name = "memory_configurator_default_linker0";

general1.$name = "CONFIG_GENERAL0";
general1.heap_size = 1048576;
general1.additional_data = "#include \"ti_enet_config.h\"";
general1.linker.$name = "TIARMCLANG0";

region1.$name = "MEMORY_REGION_CONFIGURATION0";
region1.memory_region.create(7);
region1.memory_region[0].type = "TCMA_R5F";
region1.memory_region[0].$name = "R5F_VECS";
region1.memory_region[0].auto = false;
region1.memory_region[0].size = 0x40;
region1.memory_region[1].type = "TCMA_R5F";
region1.memory_region[1].$name = "R5F_TCMA";
region1.memory_region[1].size = 0x7FC0;
region1.memory_region[2].type = "TCMB_R5F";
region1.memory_region[2].$name = "R5F_TCMB0";
region1.memory_region[2].size = 0x8000;
region1.memory_region[3].$name = "NON_CACHE_MEM";
region1.memory_region[3].auto = false;
region1.memory_region[3].manualStartAddress = 0x70078000;
region1.memory_region[3].size = 0x8000;
region1.memory_region[4].$name = "MSRAM";
region1.memory_region[4].auto = false;
region1.memory_region[4].manualStartAddress = 0x70140000;
region1.memory_region[4].size = 0x40000;
region1.memory_region[5].type = "FLASH";
region1.memory_region[5].$name = "FLASH";
region1.memory_region[5].auto = false;
region1.memory_region[5].manualStartAddress = 0x60280000;
region1.memory_region[5].size = 0x80000;
region1.memory_region[6].auto = false;
region1.memory_region[6].type = "DDR_ALL";
region1.memory_region[6].$name = "DDR_MEM";
region1.memory_region[6].size = 0x10000000;
region1.memory_region[6].manualStartAddress = 0xE0000000;

section1.$name = "Vector Table";
section1.load_memory = "R5F_VECS";
section1.group = false;
section1.output_section.create(1);
section1.output_section[0].$name = ".vectors";
section1.output_section[0].palignment = true;

section2.$name = "Text Segments";
section2.load_memory = "MSRAM";
section2.output_section.create(5);
section2.output_section[0].$name = ".text.hwi";
section2.output_section[0].palignment = true;
section2.output_section[1].$name = ".text.cache";
section2.output_section[1].palignment = true;
section2.output_section[2].$name = ".text.mpu";
section2.output_section[2].palignment = true;
section2.output_section[3].$name = ".text.boot";
section2.output_section[3].palignment = true;
section2.output_section[4].$name = ".text:abort";
section2.output_section[4].palignment = true;

section3.$name = "Code and Read-Only Data";
section3.load_memory = "DDR_MEM";
section3.output_section.create(2);
section3.output_section[0].$name = ".text";
section3.output_section[0].palignment = true;
section3.output_section[1].$name = ".rodata";
section3.output_section[1].palignment = true;

section4.$name = "Data Segment";
section4.load_memory = "DDR_MEM";
section4.output_section.create(1);
section4.output_section[0].$name = ".data";
section4.output_section[0].palignment = true;

section5.$name = "Memory Segments";
section5.load_memory = "DDR_MEM";
section5.output_section.create(3);
section5.output_section[0].$name = ".bss";
section5.output_section[0].palignment = true;
section5.output_section[0].output_sections_start = "__BSS_START";
section5.output_section[0].output_sections_end = "__BSS_END";
section5.output_section[1].$name = ".sysmem";
section5.output_section[1].palignment = true;
section5.output_section[2].$name = ".stack";
section5.output_section[2].palignment = true;

section6.$name = "Stack Segments";
section6.load_memory = "DDR_MEM";
section6.output_section.create(5);
section6.output_section[0].$name = ".irqstack";
section6.output_section[0].output_sections_start = "__IRQ_STACK_START";
section6.output_section[0].output_sections_end = "__IRQ_STACK_END";
section6.output_section[0].input_section.create(1);
section6.output_section[0].input_section[0].$name = ". = . + __IRQ_STACK_SIZE;";
section6.output_section[1].$name = ".fiqstack";
section6.output_section[1].output_sections_start = "__FIQ_STACK_START";
section6.output_section[1].output_sections_end = "__FIQ_STACK_END";
section6.output_section[1].input_section.create(1);
section6.output_section[1].input_section[0].$name = ". = . + __FIQ_STACK_SIZE;";
section6.output_section[2].$name = ".svcstack";
section6.output_section[2].output_sections_start = "__SVC_STACK_START";
section6.output_section[2].output_sections_end = "__SVC_STACK_END";
section6.output_section[2].input_section.create(1);
section6.output_section[2].input_section[0].$name = ". = . + __SVC_STACK_SIZE;";
section6.output_section[3].$name = ".abortstack";
section6.output_section[3].output_sections_start = "__ABORT_STACK_START";
section6.output_section[3].output_sections_end = "__ABORT_STACK_END";
section6.output_section[3].input_section.create(1);
section6.output_section[3].input_section[0].$name = ". = . + __ABORT_STACK_SIZE;";
section6.output_section[4].$name = ".undefinedstack";
section6.output_section[4].output_sections_start = "__UNDEFINED_STACK_START";
section6.output_section[4].output_sections_end = "__UNDEFINED_STACK_END";
section6.output_section[4].input_section.create(1);
section6.output_section[4].input_section[0].$name = ". = . + __UNDEFINED_STACK_SIZE;";

section7.$name = "Initialization and Exception Handling";
section7.load_memory = "DDR_MEM";
section7.output_section.create(3);
section7.output_section[0].$name = ".ARM.exidx";
section7.output_section[0].palignment = true;
section7.output_section[1].$name = ".init_array";
section7.output_section[1].palignment = true;
section7.output_section[2].$name = ".fini_array";
section7.output_section[2].palignment = true;

section8.$name = "User Shared Memory";
section8.type = "NOLOAD";
section8.load_memory = "USER_SHM_MEM";
section8.group = false;
section8.output_section.create(1);
section8.output_section[0].$name = ".bss.user_shared_mem";
section8.output_section[0].alignment = 0;

section9.$name = "Log Shared Memory";
section9.load_memory = "LOG_SHM_MEM";
section9.type = "NOLOAD";
section9.group = false;
section9.output_section.create(1);
section9.output_section[0].$name = ".bss.log_shared_mem";
section9.output_section[0].alignment = 0;

section10.$name = "IPC Shared Memory";
section10.type = "NOLOAD";
section10.load_memory = "RTOS_NORTOS_IPC_SHM_MEM";
section10.output_section.create(1);
section10.output_section[0].$name = ".bss.ipc_vring_mem";
section10.output_section[0].alignment = 0;

section11.$name = "Non Cacheable Memory";
section11.load_memory = "NON_CACHE_MEM";
section11.group = false;
section11.type = "NOLOAD";
section11.output_section.create(1);
section11.output_section[0].$name = ".bss.nocache";
section11.output_section[0].alignment = 0;

section12.$name = "DDR Shared Memory";
section12.type = "NOLOAD";
section12.load_memory = "DDR_SHARED_MEM";
section12.output_section.create(1);
section12.output_section[0].$name = ".bss.ddr_shared";

section13.$name = "FRAM Shared Memory";
section13.type = "NOLOAD";
section13.load_memory = "FRAM_SHARED_MEM";
section13.output_section.create(1);
section13.output_section[0].$name = ".bss.fram";

section14.$name = "FPGA Shared Regs";
section14.type = "NOLOAD";
section14.load_memory = "FPGA_REG_MEM";
section14.output_section.create(1);
section14.output_section[0].$name = ".bss.fpga_regs";

section15.$name = "FPGA Shared Archive";
section15.type = "NOLOAD";
section15.load_memory = "FPGA_ARCHIVE_MEM";
section15.output_section.create(1);
section15.output_section[0].$name = ".bss.fpga_archive";

section16.$name = "ENET Memory";
section16.type = "NOLOAD";
section16.group = false;
section16.load_memory = "MSRAM";
section16.output_section.create(3);
section16.output_section[0].$name = ".bss:ENET_DMA_OBJ_MEM";
section16.output_section[0].alignment = 128;
section16.output_section[1].$name = ".bss:ENET_DMA_PKT_INFO_MEMPOOL";
section16.output_section[1].alignment = 128;
section16.output_section[2].$name = ".bss:ENET_ICSSG_OCMC_MEM";
section16.output_section[2].alignment = 128;

enet_cpsw1.$name = "CONFIG_ENET_CPSW0";
enet_cpsw1.macAddrConfig = "Manual Entry";
enet_cpsw1.PktInfoOnlyEnable = true;
enet_cpsw1.PktInfoOnlyCount = 32;
enet_cpsw1.macport1LinkSpeed = "ENET_SPEED_100MBIT";
enet_cpsw1.macport1LinkDuplexity = "ENET_DUPLEX_FULL";
enet_cpsw1.phyToMacInterfaceMode = "RMII";
enet_cpsw1.macAddrList = "00:18:EC:FD:E7:1D,00:18:EC:FD:E7:1C:00:18:EC:FD:E7:1C";
enet_cpsw1.macport2LinkSpeed = "ENET_SPEED_100MBIT";
enet_cpsw1.macport2LinkDuplexity = "ENET_DUPLEX_FULL";
enet_cpsw1.mdioPollEnMask = [];
enet_cpsw1.mdioIsMaster = false;
enet_cpsw1.DisableMacPort2 = true;
enet_cpsw1.mdioMode = "MDIO_MODE_NORMAL";
enet_cpsw1.MDIO.MDC.$used = false;
enet_cpsw1.MDIO.MDIO.$used = false;
enet_cpsw1.txDmaChannel[0].$name = "ENET_DMA_TX_CH0";
enet_cpsw1.rxDmaChannel[0].$name = "ENET_DMA_RX_CH0";
enet_cpsw1.netifInstance.create(1);
enet_cpsw1.netifInstance[0].$name = "NETIF_INST_ID0";
enet_cpsw1.RMII.RMII_REF_CLK.$assign = "PRG0_PRU0_GPO10";

ethphy_cpsw_icssg1.$name = "CONFIG_ENET_ETHPHY0";
enet_cpsw1.ethphy1 = ethphy_cpsw_icssg1;
ethphy_cpsw_icssg1.customDeviceName = "anybusphy";
ethphy_cpsw_icssg1.phySelect = "NO-PHY";

const udma = scripting.addModule("/drivers/udma/udma", {}, false);
const udma1 = udma.addInstance({}, false);
enet_cpsw1.udmaDrv = udma1;

/**
* Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future
* version of the tool will not impact the pinmux you originally saw. These lines can be completely deleted in order to
* re-solve from scratch.
*/
gpio1.GPIO.$suggestSolution = "GPIO1";
gpio2.GPIO.$suggestSolution = "GPIO1";
gpio3.GPIO.$suggestSolution = "GPIO1";
gpio4.GPIO.$suggestSolution = "GPIO1";
i2c1.I2C.$suggestSolution = "I2C2";
i2c1.I2C.SCL.$suggestSolution = "GPMC0_CSn2";
i2c1.I2C.SDA.$suggestSolution = "GPMC0_CSn3";
mcspi1.SPI.$suggestSolution = "SPI0";
debug_log.uartLog.UART.$suggestSolution = "USART1";
debug_log.uartLog.UART.RXD.$suggestSolution = "UART1_RXD";
debug_log.uartLog.UART.TXD.$suggestSolution = "UART1_TXD";
enet_cpsw1.MDIO.$suggestSolution = "MDIO0";
enet_cpsw1.RMII.$suggestSolution = "CPSW";
enet_cpsw1.RMII.RMII1_CRS_DV.$suggestSolution = "PRG0_PRU1_GPO19";
enet_cpsw1.RMII.RMII1_RX_ER.$suggestSolution = "PRG0_PRU0_GPO9";
enet_cpsw1.RMII.RMII1_RXD0.$suggestSolution = "PRG0_PRU1_GPO7";
enet_cpsw1.RMII.RMII1_RXD1.$suggestSolution = "PRG0_PRU1_GPO9";
enet_cpsw1.RMII.RMII1_TXD0.$suggestSolution = "PRG0_PRU1_GPO10";
enet_cpsw1.RMII.RMII1_TXD1.$suggestSolution = "PRG0_PRU1_GPO17";
enet_cpsw1.RMII.RMII1_TX_EN.$suggestSolution = "PRG0_PRU1_GPO18";

0 Robert Morse 5 months ago in reply to Robert Morse

Prodigy 180 points

Ok, Part one done, turned out had to enable both MAC ports of the CPSW, then set both to no-phy, disabled the actual pins of the one not used. It now compiles.

Only thing how do I tell it that the port is up? Calling App_isNetworkUp(neftif), always returns false. So still looking into it.

Robert

0 Robert Morse 5 months ago in reply to Robert Morse

Prodigy 180 points

I must have touched something in the syscfg file, now I am back to the undefined functions. I have both MACs set again as pictured.

In the MDIO Config: what should Operating Mode be set to?

In the MDIO Config: should Master be on or off?

In the MDIO Config: should any of the Monitored PHY Addresses be enabled?

In System integration config: should External Phy Management Enable be on?

Thanks Robert

0 Nitika Verma 5 months ago in reply to Robert Morse

TI__Expert 7385 points

Hi Robert,

For enabling NO-PHY mode, you only need to make the modifications mentioned in this page - https://software-dl.ti.com/mcu-plus-sdk/esd/AM64X/latest/exports/docs/api_guide_am64x/enet_mac2mac_top.html

You can keep the MDIO settings to the default values already being used in your example and 'External Phy Management' to disabled.

Currently, MAC2MAC is not a comprehensively tested feature as mentioned in the above page, 1G full-duplex mode has been tested.

Allow me some time to test your requirement (100M full-duplex) and get back to you by next week. It might involve some modification in the Sysconfig and driver files - I will share patches for the same.

It will be helpful if you can share your current example.syscfg file as well.

Regards,

Nitika

0 Robert Morse 5 months ago in reply to Nitika Verma

Prodigy 180 points

Ok,

Here is my current syscfg file. Using MCU+ 11_00_00_15, but have tried it also with 10_01_00_32 with same results.

/**
* These arguments were used when this file was generated. They will be automatically applied on subsequent loads
* via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
* @cliArgs --device "AM64x" --part "Default" --package "ALV" --context "r5fss1-1" --product "MCU_PLUS_SDK_AM64x@11.00.00"
* @v2CliArgs --device "AM6442" --package "FCBGA (ALV)" --variant "AM6442-D" --context "r5fss1-1" --product "MCU_PLUS_SDK_AM64x@11.00.00"
* @versions {"tool":"1.22.0+3893"}
*/