PCB layout - one via per two GND/Voltage BGA balls?

Keven

Thanks for the reply.  Always nice to talk the "source".

Additionally, I'd be very interested to see how you would route the various power planes on 6 layers (assuming 2 signal, 2 GND and  2 power planes, with one power plane having a few signals on it). 

I can't possibly see how it could be done with 4 layers?.  I note the EVM has 10!!.

-steve

Steve,

I share your frustration about having a reduced layer count example to show you.  The EVM has 10 layers because it had some unique design constraints (it had to work with the DM816x daughter cards) and therefore it complicated the routing substantially.  A customer will not experience this kind of problem in a system designed for this part.

We are working on design examples with reduced layers, and have a six layer design example in the works now.  As us again in a month or so and we should be able to share more (sorry if this time table doesn't help your current project).

Can it be done in 4 layers?  Possibly, but there are a lot of questions we haven't answered yet about power routing and signal integrity, etc. that would have to be answered.  In fact, we are attempting this in a few weeks.  We'll see how it goes and hopefully shortly after the six layer design is done we'll have something to share about the four layer design.

Keven

Again vias number vs BGA power/GND balls and placement of decoupling capacitors:

I've some trouble with my board with DM3730 CUS pakage. Now I'm planning a redesign of the board and I want to be sure to have followed updated guidelines.

I've followed

http://processors.wiki.ti.com/index.php/AM37x_CUS_Routing_Guidelines

to connect Power and Ground balls to their planes, and I've placed capacitors for VDD1_MPU_IVA Net around (not underneath) the processor, like fig 21 of

http://www.ti.com/lit/an/sprabj7/sprabj7.pdf

Now I've found different guidelines

http://processors.wiki.ti.com/index.php/General_hardware_design/BGA_PCB_design/BGA_decoupling

"... share every via with two power or ground balls.  This will allow caps to fit directly underneath the part ..."

So the questions:

Is it possible to make a PCB for a DM3730 CUS package with "BGA_decoupling" guidelines and PCB Feature sizes for Via Channel(TM) BGAs ?

(rif http://processors.wiki.ti.com/index.php/General_hardware_design/BGA_PCB_design)

I want to use only through vias (no blind or buried vias), because I've the feeling that some guidelines in documents could overtake IPC-2221 and IPC-7351 rules.

AM37x_CUS_Routing_Guidelines says 3 power ball for each vias, but hasn't guidelines about capacitors placing.

If it is needed to place capacitors underneath the processor, shound I use 0201 size instead 0402 size components ?

Note: I need to add some 100nF capacitors to meet sprabj7.pdf pag 15

There are many way to route a BGA, and for most BGAs with Via Channel, via sharing is already assumed.  I wrote both the CUS routing guide and the BGA decoupling Wiki, so I can tell you the reasons behind what I said. 

The BGA decoupling Wiki describes what is possible and should always work with a regular BGA array.  If the choice is between putting decoupling caps under the footprint with shared vias, or putting the caps outside the footprint with unshared vias, I'd always choose the former (shared vias).  The inductance advantage of not sharing vias is far less than the inductance advantage of shortening the traces and putting the caps directly under the part.

While the BGA decoupling Wiki talks about sharing vias, the CUS routing guidelines show it specifically for the CUS package.  The layout there is proven, and we've built it, so we know it works.  I know the amount of via sharing there is more than usual, but the part is designed for this, and so sharing more than two vias in this case is acceptable.  This should also give more room for capacitor placement.  I didn't include capacitor placement in that guide, but there should be some good room there for some 0201 sized capacitors.  If, after the capacitors are placed with very short traces, there is room for more vias, go ahead and add them, and use the "optional" vias described in the CUS guideline too, if you can.

0402 sized capacitors are good too, but obviously less of them can be placed under the part, so they're not as good as the 0201 sized caps.  I'd always recommend using 0201 capacitors for decoupling since the inductance should be slightly lower since the body size is smaller, and you can fit more under the footprint of the BGA.  When using them, be sure to use the smallest IPC recommended footprint to avoid tombstoning as Tom Hausher recommends here: http://blogs.mentor.com/tom-hausherr/blog/2010/09/22/pcb-design-perfection-starts-in-the-cad-library-part-2/

Follow the above advice and I'm sure your design will work great.  Let me know if you have any more questions.

Keven

Thank you Keven.

What capacitor size did you use for CUS test board ? 0201 or 0402 ?

Thanks again

Best Regards

Roberto C.

There have been several CUS boards done with a layout similar to that.  The OMAP 3530, 3630, and a few other processors have the same packages, so the EVMs and any other boards that use the CUS package have used a layout similar to this (although usually on a lot of layers because the boards we build are designed to use every part of the chip).

I just pulled one up and it's 0201, and I think that's typical.  Like I said, we'd never use 0402 caps unless we had to, just because it's harder to stuff them on the board in the right area.  I understand that some assemblers don't like them because of tombstoning (where they stand up as they're being soldered) and rework, but both are manageable if done right.

Keven