I am designing DM6437 board with two 84 balls DDR2 memory. Reference to Table 4 in document SPRAAL6A, in my board X= 1.1'' and Y = 0.7'', Y offset = 0.35''.
1-Why length of A should be maximized as written in 1.1.11-DDR CK and ADDR_CTRL Routing. And how much?
2- In table 11 serial no 7 : DQ / DQS E Skew Length Mismatch maximum is 100mil. What is meant by this. What is E?
regards,
Faisal Saud