I have a question about the ULPI interface. The wiki says:
“PHY is in slave mode and the processor sources the 60MHz ULPI clock”
But the technical reference manual says it’s an input only clocked via the external transceiver.
22.1.3.1.1.3 Functional Clock
The functional clock (60MHz), USBHS_FCLK, comes from the external ULPI transceiver through the
hsusb0_clk input pin.
I think the wiki may have an error.
