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TDA4VE-Q1: TDA LPDDR4_Read Eye Mask Specification

Niranth Sagar A
Prodigy 10 points
Part Number: TDA4VE-Q1

Tool/software:

Here I am doing a LPDDR4 (3733Mbps) SI Simulation using Hyperlynx,

  1. In Read cycle we are failing with setup and hold time with the lesser margin.
  2. Currently we are using Rx eye width =0.66UI (177ps) - As per the App note "LPDDR4_Board_design_and_layout_guidelines_spracn9e"
  3. The 0.66 UI seems to be very strict Eye mask and so Measurement tool shows a marginal failure even when we have considerable eye opening.
  4. Is there any updated specification for this Data rate if so please do send us..

App Note Snip

LPDDR4_Board_design_and_layout_guidelines_spracn9e.pdf

App Note File

- This is the results of the Read Cycle from the DDR Batch report hyperlynx.

  • 0
    Prodigy 235 points

    Hi  ,

    Can u please look into the above query and provide your response ASAP..

    Thanks and regards,

    Sathish 

  • 0 in reply to Sathish Raja
    TI__Mastermind 38650 points

    Hi,

    Niranth Sagar A said:
    Is there any updated specification for this Data rate if so please do send us..

    No, the required diamond shaped read eye mask for LPDDR4-3733 has not changed from 0.66 UI / 120 mV.

    The latest version of the document can be found under technical documentation from the product page. Here is the link: https://www.ti.com/lit/pdf/spracn9 

    Niranth Sagar A said:
    In Read cycle we are failing with setup and hold time with the lesser margin.

    How does Hyperlynx determine setup / hold requirements, and what are they set to?

    Are you able to visually see the data eye and overlay the required eye mask?

    Regards,
    Kevin

  • 0 in reply to Kevin S
    Prodigy 235 points

    Hi Kevin,

    The Hyperlynx calculates required Setup/Hold time from the Timing model defined.

    Below is the calculation by which Setup Requirement is considered by Hyperlynx.

    Yes, we are able to see the Eye diagram (as seen below) and it has considerable opening but considering the Output Variation (-42.8 ps)Parameter as per DRAM timing model we couldn't meet the Setup/Hold requirement.

    Actual Setup time  = Setup time Measured + Output Variation = 128ps - 42.8ps = 85.2ps 

    Margin = 85.2ps - 88.4ps = -3.2ps .

    Thanks and regards,

    Sathish

  • 0 in reply to Sathish Raja
    TI__Mastermind 38650 points

    Hi,

    Thanks for these details. My understanding is that the READ eye mask we document already includes the DRAM output variation. In other words, there is no need to further reduce the measured width of the simulated eye when comparing to the READ eye mask.

    Regards,
    Kevin

  • 0 in reply to Kevin S
    Prodigy 235 points

    Hi Kevin,

    Thanks for your reply.

    Then with Output variation coming from DRAM timing model I can consider 50% UI (134.2ps) instead of 66% UI (177ps) as Read eye mask...for my simulations.

    ie.,66% UI = 177ps - 42.8ps = 134.ps (50% UI)

    Is my understanding correct??

    Thanks and regards,

    Sathish