SK-AM62A-LP: MCU Timer 0 clock configuration

Hi,

Please let me know if this helps you: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1494228/sk-am62a-lp-autosar-integration-on-mcu-r5f-core/5790031#5790031

Please let me know if you are able to reach a stage where I am in the diagram as mentioned in the response and you also see 80 MHz.

Looking forward to your response.

Regards,

Vaibhav

Hi Vaibhav,

Thanks for the quick response. Yes i have reached the stage where you are currently. I can see 80 MHz 

Regards,

Nikhil

Hi Nikhil,

Glad to know you have reached the same point as me.

From here onwards, we need to figure out the register spaces where these changes need to go in.

Can you do this part, at the same time I am going to try it on my own setup as well.

Regards,

Vaibhav

Hello Nikhil,

I have reviewed the clock tree configuration related to MCU Timer 0, and wanted to share my understanding and recommendation.

Timer 0 receives its clock through a MUX with multiple source options. 
• Option 0: 25 MHz from HFOSC
• Option 1: MCU_SYSCLK / 2, which currently results in 200 MHz (assuming MCU_SYSCLK is 400 MHz)

If your target is to run the timer at 80MHz, this would require reducing MCU_SYSCLK to 160 MHz.

However, please note:
• MCU_SYSCLK feeds several critical modules, including other IPs, PLLs, and the CPU core itself.
• Lowering MCU_SYSCLK from 400 MHz to 160 MHz would significantly degrade overall system performance.
• Therefore, modifying MCU_SYSCLK is not recommended.

Other clock source options like PLL changing and Internal RC oscillator changes are not recommended .

• Option 5: Using an external clock is a viable solution. For example, if you feed in an 80 MHz clock externally, it can meet your timing requirements without affecting other system clocks.

Timer Resolution Considerations:
• If Timer 0 runs at 25 MHz, the resolution is 0.04 µs
• If it runs at 80 MHz, the resolution improves to 0.0125 µs

However, in most software use cases such as task scheduling (typically in the microsecond, millisecond, or second range), 25 MHz clock should be acceptable for your use case.

Request for Clarification:

To better assist, could you please share the exact use case or reason behind requiring a specific timer frequency? That would help us evaluate further and propose the best-fit solution.

https://dev.ti.com/sysconfig/#/config/?args=--product%20%2Fmnt%2Ftirex-content%2Fsitara_ctt_1_1_4%2F.metadata%2Fproduct.json%20--device%20AM62A7%20--package%20%22FCBGA%20P$OPEN$AMBP$CLOSE$%22%20--variant%20AM62A74-M%20--context%20system

Regards,

Anil.