TDA4VL-Q1: TDA4VL-Q1: Partial problem confirmation of WDG module in MCAL

Hello，

2）Are you sure why it can't be configured as reset?

I can't reply to you on the latest post

Hi Kong,

I raised an internal ticket couple of days back (https://jira.itg.ti.com/browse/MCAL-30607) and am waiting for their reply .I will post you the updates as soon as i get.

Regards

Tarun Mukesh

Hi：

May I ask if you have confirmed why WDG cannot be configured to reset mode

hi：

In the TRM manual, I saw that a reset signal can be generated in the RIT diagram. Is this reset signal also known as an interrupt signal?

In the window watchdog, it is also proposed that feeding the dog outside the window will generate NMI or reset

Hello,

RTI is a down-counter that count from non-zero value to zero and generates an interrupt to CPU or ESM which in-turn could be programmed to reset the SoC.

You can see this decision taken in implementation

https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/07_03_00_07/exports/docs/mcusw/mcal_drv/docs/drv_docs/design_wdg_top.html#:~:text=Watchdog%20SOC%20Reset%20Functionality

Regards

Tarun Mukesh

Hi，

So should the description of RTI be confirmed in the above document, rather than in the TRM manual?

There is another question I would like to confirm. In the register table, the default value of WWDRXN is 5, which means that a watchdog overflow will result in a reset. If a reset cannot be generated and the register is not modified, an interrupt will also be generated after the watchdog overflow?

Thanks