Tool/software:
I am testing the configurations I shared above, along with some different combinations.
I can successfully receive the data sent from the SPI master — I verify this by checking the SPIFLG flags and reading the received data directly from the SPIBUF register.
However, the DMAX event does not seem to trigger, or DMAX does not perform the transfer into the buffer whose address I have provided.
Since I can confirm that the SPI Slave is correctly receiving data, I am assuming the SPI and DMAX configurations are correct.
I suspect that the issue might be related to my interrupt setup. Sometimes, my code crashes, which makes me believe there could be a mistake in how I configured the interrupts.
Could you please help me understand where I might be making a mistake in the interrupt configuration?
I would really appreciate any guidance or suggestions you could provide.
Thank you in advance for your support!
/*1- dMAX event High priority*/
dMax_ptr[DEHPR]= 0x2000; // event 13 set a High priority
/*2- dMAX Event polarity */
dMax_ptr[DEPR] = 0x2000; // event flag is set on falling(0) edge
/* PaRAM SPI Slave Transfer
*
* bit 4-0 =ETYPE = 0b00010 // event type: SPI slave data transfer
* bit 5 =RLOAD = 0b1 // Reload Active counter
* bit 7-6 =ESIZE = 0b10 // 16-bit Element
* bit 23-8 =PTE = 0x1d4 // pointer to transfer entry // transfer entry-7
* bit 27-24 =TCC = 15-0 // Transfer Complete Code.
* bit 28 =TCINT = 0b1 // After completing a whole transfer, the dMAX controller sets a TCC pending bit and triggers an interrupt to the CPU.
* bit 29 =SPI = 0b0 // SPI0 Selection
* bit 31-30 =reserved
*
* = 0x1001D4A2
* */
dMaxEvent_ptr[13]= 0x1001D4A2; // event entry 13
/*
* dmax transfer entry for spi slave transfer
* fixed 11 word
*
* word 0 = bit 31-0 = SRC Address(active) = Source address
* word 1 = bit 31-0 = DST Address(active) = Destination address
* word 2 = bit 31 = PP = Referance bit
* bit 30-16 =reserved
* bit 15-0 = COUNT(active) = Count in unit of elements - updated by the dMAX controller during course of transfer
* word 3 = bit 31-16 reserved
* bit 15-0 = COUNT (referance) =Reference Count in unit of elements.
* word 4 = bit 31-0 = SRC RELOAD ADDRESS0 = Source Address Reload 0
* word 5 = bit 31-0 = DST RELOAD ADDRESS0 = Destination Address Reload 0
* word 6 = bit 31-0 = SRC RELOAD ADDRESS1 = Source Address Reload 1
* word 7 = bit 31-0 = DST RELOAD ADDRESS1 = Destination Address Reload 1
* word 8-10 = reserved
*
*
* */
/*4- Transfer entry configured */
dMaxTransfer_ptr[0] = (unsigned int)dmaxTxData; // transfer entry 7 word0
dMaxTransfer_ptr[1] = (unsigned int)dmaxRxData; // transfer entry 7 word1
dMaxTransfer_ptr[2] = (unsigned int)0x0f; // transfer entry 7 word2 // 16 uzunluk
dMaxTransfer_ptr[3] = (unsigned int)0x0f; // transfer entry 7 word3
dMaxTransfer_ptr[4] = (unsigned int)dmaxTxData2; // transfer entry 7 word4
dMaxTransfer_ptr[5] = (unsigned int)dmaxRxData2; // transfer entry 7 word5
dMaxTransfer_ptr[6] = (unsigned int)dmaxTxData; // transfer entry 7 word6
dMaxTransfer_ptr[7] = (unsigned int)dmaxRxData; // transfer entry 7 word7
/* Setting up the DMAX Interrupts */
/* Interrupt Initialization */
status_int = CSL_intcInit (&intcContext);
if (status_int != CSL_SOK) {
dmax_error_exit ();
return status_int;
}
status_int = CSL_intcDispatcherInit (&intcDispatcherContext);
if (status_int != CSL_SOK) {
dmax_error_exit ();
return status_int;
}
/* Install handler for DMAX INT8 Interrupt */
hIntc = CSL_intcOpen (&intcObj,
CSL_INTC_EVENTID_DMAXEVTOUT1, NULL, &status_int);
if ((hIntc == NULL) || (status_int != CSL_SOK)) {
status_int = CSL_ESYS_BADHANDLE;
dmax_error_exit();
return status_int ;
}
isrRec.handler = intr08;
/* As no arguments assigning zero(0) value */
isrRec.arg = (void *) 0x0;
/*Plugging ISR in Event Handler */
CSL_intcPlugEventHandler (hIntc, &isrRec);
/* Enabling DMAXEVTSPI Event */
status_int = CSL_intcEventEnable (CSL_INTC_EVENTID_DMAXEVTOUT1, &eventStat); // SPI ayarlandı
if (status_int != CSL_SOK) {
dmax_error_exit ();
return status_int;
}
/* Enabling Non-Maskable Interrupt */
status_int = CSL_intcEventEnable (CSL_INTC_EVENTID_NMI, &eventStat);
if (status_int != CSL_SOK) {
dmax_error_exit ();
return status_int;
}
/* Enabling Global Enable bit in Control Status Register (CSR) */
status_int = CSL_intcGlobalEnable (&state);
if (status_int != CSL_SOK) {
dmax_error_exit ();
return status_int;
}
/* Closing INTC Handle */
status_int = CSL_intcClose (hIntc);
if (status_int != CSL_SOK) {
dmax_error_exit ();
return status_int;
}
/* Setting up the DMAX Interrupts */
/*5- dMAX event enable*/
dMax_ptr[DEER]= 0x2000; // event 13
pinmsk = 0x0E01; /* SPI 4-pin with chip select mode */
/* 1. Take the SPI0 out of reset */
spi0_ptr[SPIGCR0] = 0x01;
/* 2. Configure SPI0 for slave */
spi0_ptr[SPIGCR1] = 0x00;
/* 3. Configure SPI0 mode */
spi0_ptr[SPIPC0] = pinmsk;
/* 4. Chose SPI0SPIFMT0 */
spi0_ptr[SPIDAT1] = 0x00000000;
/* 5. Configure SPI0 for SHIFTDIR=0,POLARITY=1,PHASE=0,
CHARLEN=16 */
spi0_ptr[SPIFMT0] = 0x00001410;
/* 6. SPIDELAY for SPI0 not relevant in slave mode */
spi0_ptr[SPIDELAY] = 0x00;
/* 7. Configure SPI0 for error notifications for OVR,BITERR and DESEL */
//spi0_ptr[SPIINT0] = 0x00000054;
spi0_ptr[SPIINT0] = 0x00000000;
spi0_ptr[SPILVL] = 0x00;
/* 8. Enable SPI0 communication */
spi0_ptr[SPIGCR1] |= 0x01000000;
/* 9. Configure SPI0 for dmax servicing of spi events*/
spi0_ptr[SPIINT0] |= 0x00010000;
