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EDMA3 and cache

Mads Lind Christiansen
Expert 1130 points

Other Parts Discussed in Thread: OMAP-L138

Hi

Just a quick question. Our HW is the OMAP-L138.

We are doing EDMA3 transfers from L2RAM to EMIFA, these are triggered manually. 
I need to know if it is required to do a BCACHE_wb (cache writeback with wait) before initiating the EDMA3 transfer to avoid a cache coherence problem?

/Mads

 

 

  • 0
    TI__Guru 56637 points

    Mads,


    No you don't since L2 SRAM is maintained as hardware coherent with the L1 cache.

    If the transfer were the other way around (EMIF->L2RAM), and the data buffer in EMIF is touched/modified by the CPU, then you would need to do a Write-Back command to ensure the EDMA picks up the latest data.  This is because automatic coherence is NOT maintained for the EMIF address range.  

     

    Regards

    Kyle

  • 0 in reply to kcastille
    Expert 1130 points

    Hi Kyle

    Many thanks for this answer. I have read a lot of TI docs. but couldn't seem to find this anywhere. But I sort of also concluded what you have stated (since doing a cache wb did not make any difference in my cache besides a performance loss due to wb wait).

    One more quick question. If I (for some odd reason) wish to do EDMA3 transfers from cached EMIFA/DDR area to L2RAM I would need to do a cache wb, but would it also be necessary to do a cache write back with wait, or could I just initiate the wb (without wait) and then start the EDMA transfer?

     

    Thanks for answering my other question, I will accept it as an answer.

     

    Best wishes,
    Mads

  • 0 in reply to Mads Lind Christiansen
    TI__Guru* 85835 points

    Mads

    Kyle is out of office. 

    For your query on use of the API's with and without wait, please look at the description provided in the user guides like

    http://www.ti.com/lit/ug/spruex3j/spruex3j.pdf (Section 7.4.1)

    and 

    http://www.ti.com/lit/ug/sprug82a/sprug82a.pdf (Section 2.4.2.2)

    Hope this helps.

    Regards

    Mukul 

  • 0 in reply to Mukul Bhatnagar
    TI__Guru 56637 points

    You will need to wait.  This will guarantee the EDMA will get the latest data i.e., AFTER it is "written back" to the DDR address.

     

    Regards
    Kyle