• State
  • Locked Locked
  • Replies 3 replies
  • Subscribers 99 subscribers
  • Views 166 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TDA4AH-Q1: DSPLib Test Documentation

rperezti
Genius 12670 points
Part Number: TDA4AH-Q1

Tool/software:

Hi we are evaluating DSPLib from Processor SDK RTOS J784S4 v10.01. The DSPLIB examples are simple and easy to understand. However, DSPLIB tests look to be a bit involved by including many test scenarios in each module test. Is there documentation that can help me understand the test scenarios of each DSPLIB module’s test?

  • 0
    TI__Expert 6920 points

    Hi,

    I will check if there is any documentation for the same and update in this thread.

    Regards,
    Sivadeep

  • 0 in reply to Sivadeep P R
    TI__Genius 12670 points

    Hi Sivadeep. Can you provide an update on this?

  • 0 in reply to rperezti
    TI__Expert 6920 points

    Hi,


    I was not able to find any official document, but the test folder structure is generally consistent across kernels. It includes files like d.c, idata.c, idata.h, a CSV file, and gendata.py.


    idata.h: Defines a struct with all input arguments for testing.
    idata.c: Auto-generated using gendata.py, containing test cases based on the struct.
    d.c: The main test wrapper that handles memory allocation, runs both natural C and optimized versions, and compares results.
    gendata.py: Python script used to generate idata.c.


    Test types:


    STATIC: Use predefined inputs (hardcoded or from a CSV file).
    RANDOM: Inputs are generated at runtime to test robustness.

    Regards,
    Sivadeep.