Tool/software:
Hello,
After trying to implement a 10G USXGMII link in MAC2MAC on SerDes 2 (in a multilink configuration with an SGMII refclk @100MHz with internal_refclk1 and USXGMII with an external refclk @ 156.25MHz), I spotted in a bug in the current CSL_SerdesEnableLanes function, in csl_serdes3.c.
The function never checks the refclk source and therefore sets a potentially bad value in the Pn_MAC_SRC_CLK and Pn_REFCLK_SRC fields of LANECTLn registers of the WIZ wrapper, depending on the source of the actual refclk. For my use case in USXGMII, it sets the value of Pn_MAC_SRC_CLK @ 0x2, which is derived from REFCLK_INT0 (which I do not set as a refclk), regardless of where my clock is coming from. In the case where one may want to use the external refclk, that would cause trouble on the lane selected for USXGMII. This applies to the Pn_TXFCLK_SEL field as well, which is never set in the PDK functions.
I hope this post allows a change request to be made available for future releases, because of the sheer lack of documentation available for the SerDes.
Best regards,
Arthur
Arthur Odin