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C6474 CACHE configuring code request.

Tom Smith
Expert 2930 points


We are looking into enabling the cache memory (L2) in our MX platform. We use the entire internal memory as an SRAM in our current architecture and we think we should start using a part of it as a cache.  Can you get us a sample code for configuring this memory?  This will save us lots of time.

-Tom-

  • 0
    TI__Guru* 84110 points

    Tom,

    The MCSDK 1.0 should have the example code that you need. Go to the TI Wiki Pages and search on MCSDK.

    Actually, the GEL files that come with the C6474 EVM should also have sample code that is similar to C that shows how you can configure it.

    Also, the C6474 CSL offers commands for configuring the cache. You can also find that on the Wiki, search on "C6474 CSL" (no quotes).

    Regards,
    RandyP

     

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