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LCDC DONE interrupt problem

we are using the LCDC to transfer data to another device.  our device produces video frames at varying rates from almost 0 to 100 Hz depending on customer input.  I want the video frames to come out at whatever rate they are produced by the customer.  to do this I am enabling and disabling the RASTER_EN in the RASTER_CTRL register.  I enable the DONE_EN interrupt to detect when the transfer is complete. it takes about 10 ms to transfer our video frame.

but...for some reason I am getting 3 DONE interrupts for every time I send a frame.  here is the basic sequence:

clear DONE in LCD_STAT
enable DONE_EN in RASTER_CTRL
enable RASTER_EN in RASTER_CTRL
<a couple of housekeeping statements>
disable RASTER_EN in RASTER_CTRL (the controller will finish the frame after starting)
...
HW interrupt #1
TSCL says it has been 5 us since the transfer started
LCD_STAT==0x00000001
RASTER_CTRL==0x00000088
acknowledge interrupt and return
...
HW interrupt #2
TSCL says it has been 1-2 us since the last HW interrupt
LCD_STAT==0x00000001
RASTER_CTRL==0x00000089
acknowledge interrupt and return
...
HW interrupt #3
TSCL says it has been 10 ms since the last HW interrupt
LCD_STAT==0x00000141
RASTER_CTRL==0x00000088
acknowledge interrupt and return
...
repeat until tired

after extensive text searching I believe there is only one place where I set the DONE_EN bit in RASTER_CTRL, yet it is always on when I get an interrupt. I tried setting a watchpoint but it never breaks despite the fact I am writing RASTER_CTRL all the time

also, the RASTER_EN bit is NOT on when I receive the first HW interrupt, but it IS on when I receive the second HW interrupt - how can that be?

in my current setup video is going out at 50 Hz. is there a problem using the LCDC is this way? or am I missing something here?

  • Hi Kurt,

    The LCDC is really meant to be used in a synchronous fashion...

    I will check with design on the exact condition that "DONE" is set.

    So you are using Raster TFT mode, correct? what's the BPP? In this mode, the LCDC DMA grabs data for the palette first, and I suspect the first two interrups are related to that. I believe the 3rd interrupt is really for the transfer of that frame as EOF0 is set as well.

    Do you get 3 interrupt consistently everytime you transfer? If you double the size of your frame buffer, does the clock reading for interrupt1/2 change? does the clock reading for interrupt 3 double?

    It would be much more helpful if you could tell whether the data transfer only start after interrupt 2 or not.

    regards,

    Paul

  • yeah, well, I'm just the software guy...

    yes, Raster TFT mode - 16 BPP

    I do not get 3 interrupts consistently... sometimes I get 1 interrupt, sometimes I get 2 - in both cases LCD_STAT==0x00000001, i.e. I do not ever see EOF0.  I tried to tie my stuff to EOF0 but then I get this second problem. now I have a major kludge just so my code keeps running.

    clock reading for interrupt1/2 does not change

    data transfer always starts after interrupt 2.

  • in case anyone was wondering...

    apparently the LCDC is sending out 2 spurious interrupts on setting RASTER_EN.  if I disable hardware interrupts until after I set RASTER_EN then I do not see the 2 early interrupts, i only see one interrupt after the transfer is complete