TDA4VE-Q1: ESM event mapping into groups

Pramod Lakshman

Part Number: TDA4VE-Q1
Other Parts Discussed in Thread: TDA4VL

Tool/software:

Dear TI Team,

We are using the TDA4VL/TDA4AL SoCs in our projects, and as part of the safety requirements we would like to configure and enable ESM.
I read through the TRM regarding the ESM module initialization, but some information mentioned below are bit contradicting.

It is mentioned in the TRM that the ESM input events are grouped in 32.
So each configuration register for a group j is a 32 bit register, with each bit representing the configuration for an ESM event.

For example, we consider the description of ESM_INTR_SET_EN_j register,

Here j = 0 to 3, so 4 groups for WKUP and MCU ESM instances, and 0 to 7 for Main ESM instance.
This means number of groups are 4 for the WKUP_ESM and MCU_ESM instances, and 8 groups for Main ESM instance.

This means we have upto 128 (4*32) ESM input events for the WKUP and MCU instances, and 256 (8*32) ESM input events for the main ESM instance.

In the interrupt sources section in TRM, I see that there are total
- 128 (interrupt IDs 0 to 127) events for WKUP ESM instance
- 105 (interrupt IDs 0 to 105) events for MCU ESM instance
- 666 (interrupt IDs 0 to 665) events for Main ESM instance

It is not clear to me how the 666 events of Main ESM instance is mapped in 8 groups.

Could you please confirm if my understanding is correct, or I missed something, and provide me a detailed description of how the ESM events are mapped to the configuration registers?
Thank you!

Best Regards,
Pramod Lakshman

over 1 year ago

0 Pramod Lakshman over 1 year ago

Intellectual 550 points

Adding to the above info:
I checked the ESM related function implementation/examples in the SDL (version 10.1).
And there the maximum number of groups are considered to be 32, thus resulting in 32*32 = 1024 events.

In the implementation of this function in SDL, I see that all 32 bits of the ESM_ERR_STS register is able to be programmed, to clear any errors.

/**
 *  Design: PROC_SDL-2010
 */
int32_t SDL_ESM_clearCfgIntrStatus(uint32_t baseAddr, uint32_t group)
{
    int32_t  retVal = SDL_EBADARGS;
    uint32_t regVal = 0U;
    if ( (baseAddr != ((uint32_t) (0u))) &&
         (group < ESM_INTR_GRP_NUM))
    {
        regVal = ((uint32_t) 0x1U << (group));
        HW_WR_REG32(baseAddr + SDL_ESM_ERR_STS, regVal);
        retVal = SDL_PASS;
    }
    return retVal;
}

But in the TRM, I see the description of this register states that only bits 0 to 7 can be programmed, and the remaining bits are reserved.

So according to this description, maximum number of groups is 8, where as according to the SDL examples 32 groups are assumed.
Could you please check and confirm the maximum number of ESM input event groups, and also provide a table indicating the mapping of these events to the configuration registers?

Thank you!

Best Regards,
Pramod Lakshman

+1 Josiitaa RL over 1 year ago

TI__Guru 57191 points

Hi Pramod,

Please refer o the latest TRM available on ti.com - https://www.ti.com/lit/zip/spruj28

The register descriptions have been moved to the j721s2_Registers_Public_20250116.xlsx where the value of j for the ESM registers has been updated as below -

Your understanding of how the ESM events are mapped to the registers is correct.

Regards,

Josiitaa

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TDA4VE-Q1: ESM event mapping into groups