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AM6442: HS200 compliance test failing on the clock

Valentin LE GUELVOUIT
Prodigy 60 points
Part Number: AM6442

Tool/software:

Dear e2e team,

I hope this message finds you well. We are currently running a HS200 compliance test on our product for our eMMC. This test is performed using a dedicated compliance module of our oscilloscope (RTO6 K92 option).

We are currently failing the clock's period test. According to the JEDEC JESD84-B51 standard, the minimum value must satisfy : Tclock >= 5ns.The procedure is the following : acquire 1000 periods and take the minimum value out of these at room humidty and temperature.

Amongst 8 runs of tests (8*1000 periods) there are always a few of them being below the 5ns (4.969 ns for instance). From what I could tell, this is reflected when performing a frequency analysis where you see that some sort of jitter is bringing the frequency slightly higher than the 200MHz.

Since the AM64 is sold as HS200 compliant, could you share with us a report showcasing the test conditions but also sharing your thoughts on our problem?

Thanks in advance.

Best,

  • 0
    TI__Guru 62855 points

    The 5ns min clock period defined for the AM64x device is an average min period. There will be a few clock cycles that are less than 5ns and a few clock cycles that are longer than 5ns when operating CLK at 200MHz, due to PLL jitter. The PLL is constantly adjusting its output frequency as it tracks a multiple of the input reference clock. The PLL jitter doesn't cause a problem for either device because the design team accounts for the worst-case variation of PLL output frequency when they close timing for each peripheral.

    The primary concern for the attached device is providing enough setup/hold time for data transfers during these short clock periods. This was accounted for during timing closure, so you should not encounter a problem with these short clock cycles.  

    It would be necessary to reduce the operating frequency to ensure the clock period is never less than 5ns for any single clock cycle. Most customers are no willing to lose the bandwidth associated with a reduction in operating frequency.

    Regards,
    Paul

  • 0 in reply to peaves
    Prodigy 60 points

    Dear Peaves,

    Thank you for taking the time answering my question. I understand that the current implementation was to maximize the output data rate.

    However, I could not find any clue about the "average min period" you are referring to. I triple checked the standard and it is not mentionned. On the contrary, there are references to the fact that the frequency SHALL NOT exceed 200MHz.

    Although I understand your point of view (your implementation makes sense to me) and it is not a technical blocker for us, I think it is also fair to say that the AM6442 does not meet 100% of the standard requirements with a PLL at 200MHz. It would be necessary to decrease it to ensure that we meet the requirements fully. If you agree with this, the topic can be closed in my opinion.

    Best,

  • +1 in reply to Valentin LE GUELVOUIT
    TI__Guru 62855 points

    I agree, the AM64x eMMC clock period can be less than 5ns and some eMMC devices may consider this a spec violation. However, this is not likely to cause any problems for the attached device since we provide enough setup/hold margin even when the PLL jitter creates an occasional short clock period.

    Regards,
    Paul