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tvp514xm2 video standard exchange questions at DM37X platform board

joi huang
Intellectual 350 points
Other Parts Discussed in Thread: TVP5146M2, TVP5146

Now,I am developing a capture to preview solution at DM37X platform board,
and I have few tvp514xm2 video standard exchange questions which need your support,
could you give me a hand ? thanks ,the following are my questions

1.as I know,at tvp5146m2 spec . I can see a PIN "IRQREQ" ,If I wannt to trigger a "INTREQ"
  when video standard exchanged,How can I do it ?
  Because I have set the Register Interrupt Mask 1 Register[bit1]Standard changed,
                        and Register Interrupt Clear 1 Register[bit1] Standard changed as "1",
  but when video Standard has been changed (ex:ntsc-m changed to pal-N;or pal-bdghi changed to pal-Nc),
  it can't generate a INTREQ signal
 
  the following are related registers -->
  REG_VIDEO_STD=0x2
  REG_AUTOSWITCH_MASK=0x3f
  REG_VIDEO_STD_STATUS=0x2
  REG_INTERRUPT_RAW_STATUS0=0x0
  REG_INTERRUPT_RAW_STATUS1=0x0
  REG_INTERRUPT_STATUS0=0
  REG_INTERRUPT_STATUS1=0
  REG_INTERRUPT_MASK0=0
  REG_INTERRUPT_MASK1=2
  REG_INTERRUPT_CLEAR0=0
  REG_INTERRUPT_CLEAR1=0
 


2.Does the Register "Video Standard Status Register(0x3F)" dynamically show correct video standard
  If video standard has been exchanged ?
 
  Because when the video exchanged from NTSC-M to NTSC-443,and I do a program to read the related registers,
  the register REG_VIDEO_STD still show 0x2 but not 0x5;
 
  the following are related registers -->
 
  REG_VIDEO_STD=0x2
  REG_AUTOSWITCH_MASK=0x3f
  REG_VIDEO_STD_STATUS=0x2
  REG_INTERRUPT_RAW_STATUS0=0x0
  REG_INTERRUPT_RAW_STATUS1=0x0
  REG_INTERRUPT_STATUS0=0
  REG_INTERRUPT_STATUS1=0
  REG_INTERRUPT_MASK0=0
  REG_INTERRUPT_MASK1=2
  REG_INTERRUPT_CLEAR0=0
  REG_INTERRUPT_CLEAR1=0
  

  • 0
    TI__Expert 8180 points

    Hi,

      REG_VIDEO_STD=0x2

    This looks weird to me, isn't this should be in auto-switch mode? you are forcing it to one standard here.

      REG_AUTOSWITCH_MASK=0x3f
      REG_VIDEO_STD_STATUS=0x2

    Here bit7 should be '1', which again depends on REG_VIDEO_STD configuration.

      REG_INTERRUPT_RAW_STATUS0=0x0
      REG_INTERRUPT_RAW_STATUS1=0x0
      REG_INTERRUPT_STATUS0=0
      REG_INTERRUPT_STATUS1=0
      REG_INTERRUPT_MASK0=0
      REG_INTERRUPT_MASK1=2
      REG_INTERRUPT_CLEAR0=0
      REG_INTERRUPT_CLEAR1=0

    So certainly you are not configuring TVP5146 to autoswitch mode and result is in sync with what you are seeing.

    Thanks,

    Vaibhav

  • 0 in reply to Vaibhav Hiremath
    Intellectual 350 points

    Hello Vaibhav,

    thanks for your reply,

    after setting tvp514xm2 register Video Standard Register (0x02)  to 0x00 ,and

                                                               REG_AUTOSWITCH_MASK(0x04) to 0x3f ,

    If Input Video standard has been exchanged ,

    I can polling the related register  "REG_VIDEO_STD_STATUS(0x3F)" ,and it will show different state

    for example:

    if video standard has been exchanged from PAL-dbghi to PAL-nc ,the related registers will changed

    from

    REG_AUTOSWITCH_MASK=0x3f
    REG_VIDEO_STD_STATUS=0x82
    REG_INTERRUPT_RAW_STATUS0=0x0
    REG_INTERRUPT_RAW_STATUS1=0x0
    REG_INTERRUPT_STATUS0=0
    REG_INTERRUPT_STATUS1=0
    REG_INTERRUPT_MASK0=0
    REG_INTERRUPT_MASK1=2
    REG_INTERRUPT_CLEAR0=0
    REG_INTERRUPT_CLEAR1=0

    to

    REG_AUTOSWITCH_MASK=0x3f
    REG_VIDEO_STD_STATUS=0x84
    REG_INTERRUPT_RAW_STATUS0=0x0
    REG_INTERRUPT_RAW_STATUS1=0x0
    REG_INTERRUPT_STATUS0=0
    REG_INTERRUPT_STATUS1=0
    REG_INTERRUPT_MASK0=0
    REG_INTERRUPT_MASK1=2
    REG_INTERRUPT_CLEAR0=0
    REG_INTERRUPT_CLEAR1=0

    so,it seems ok ,for polling the "REG_VIDEO_STD_STATUS(0x3F)"  to know video standard exchanged

    and,another question is  that Can we trigger INTIRQ(tvp514xm2) if video standard exchanged ?

    Thanks ~ 

     

     

     

  • 0 in reply to joi huang
    TI__Expert 8180 points

    Good to hear that, now things are working fine for you.

    As far as INTIRQ for STD change is concerned, yes certainly you can configure TVP5146 for this. Unmask/Set the bit.1 of INTERRUPT_MASK1.

    Thanks,

    Vaibhav

  • 0 in reply to Vaibhav Hiremath
    Intellectual 350 points

    Hi Vaibhav Hiremath,

    thanks for yor reply very much,

    For trigger a interrupt at INTREQ of tvp514xm2 when video standard exchanged,

    after Unmask/Set the bit.1 of INTERRUPT_MASK1,I still can not trigger this pin  INTREQ of tvp514xm2 ,

      the following are related registers -->
      REG_VIDEO_STD=0x0
      REG_AUTOSWITCH_MASK=0x3f
      REG_VIDEO_STD_STATUS=0x81
      REG_INTERRUPT_RAW_STATUS0=0x0
      REG_INTERRUPT_RAW_STATUS1=0x0
      REG_INTERRUPT_STATUS0=0
      REG_INTERRUPT_STATUS1=0
      REG_INTERRUPT_MASK0=0
      REG_INTERRUPT_MASK1=2
      REG_INTERRUPT_CLEAR0=0
      REG_INTERRUPT_CLEAR1=0

    by the way,I have post the similar question at TI e2e forum,tags:tvp5146m2

    the attached link as following:

    http://e2e.ti.com/support/dsp/sitara_arm174_microprocessors/f/416/t/150990.aspx 

    Best Regards