Tool/software:
We flashed the new complied kernel to the hydra board but find accessing FPGA register does not work well.
After some investigation we find GPMC FCLK does not have output on GPMC0_FCLK_MUX.
We set the clock according to https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j7200/clocks.html
power-domains = <&k3_pds 115 1>;
clocks = <&k3_clks 115 0>;
clock-names = "fck";
Detailed changes can be found here https://gitlab.apps.ge-healthcare.net/212743540/hydra_bsp/-/commits/gpmc-debug
We also tested the SYSCLKOUT0(Pin V1) MCU_SYSCLKOUT0(Pin C20 )and MCU_OBSCLK0 (Pin C16), they also have no output. I think these clocks should work well.
Could you please test at your side the output of these clock pins and share what additional configuration is needed to make the clock output work well? Thanks a lot.
Besides testing the clock signal with the Oscilloscope, we also read out the related clock config registers as below.
We find these registers value is same in uboot and kernel, and enabling the GPMC driver does not change CTRLMMR_GPMC_CLKSEL, is this expected?
|
Register Name/Addr. |
CTRLMMR_WKUP_MAIN_PLL0_CLKSEL 0x43008080 |
PLL0_HISDIV_CTRL3 0x0068008C |
CTRLMMR_GPMC_CLKSEL 0x001080D0 |
|
Value |
00800000(bit23) |
0000800e(bit15, enable clk out1, ) |
00000000 |
