Tool/software:
Could you confirm that "internal reference clk" mentioned here, TDA4VH-Q1: SERDES REFCLK PPM - Processors forum - Processors - TI E2E support forums,
is referring to the fact that also SGMII interface have been validated by using internal PLLs and buffers within the SoC that is clocked only by an external oscillator connected to WKUP_OSC0? Meaning, SGMII is validated without using external SERDES clock?