• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 98 subscribers
  • Views 132 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320C6678: cache flush/invalidate optimization

Alberto Chessa
Mastermind 6670 points
Part Number: TMS320C6678


Tool/software:

Hi,

There is a way to optimize cache flush and invaliate operations?

If I produce 8MB bytes of data, written in DDR, and I want to pass them to another core, a cache flush i required. Normally I flush form data start up to data start + size (1M), but since the cache is 512M only, I would like to flush 512K only.

If the data are produced in sequence, from lower address to upper address, can I assume only the last 512K of data requires flush?

  • 0
    TI__Expert 4500 points

    Hi Alberto,

    For quick reference: https://www.ti.com/lit/ug/sprugy8/sprugy8.pdf

    In Chapter 3, "Optimizing for Cache Performance," outlines various cache optimization strategies, and the following sections cover:

    1. Section 3.2.3: provides an overview of optimization techniques.

    2. Sections 3.3 and 3.4 detail application-level and procedural-level optimizations, outlining key considerations to achieve optimal cache performance.

    The C6678 utilizes an LRU(Least Recently Used allocation) replacement policy per set. Thus, when the volume of data written exceeds the cache capacity, the oldest data is automatically evicted to accommodate new data. During sequential data writes, it is generally sufficient to flush only the portion of memory that may still reside in the cache.

    Best Regards,

    Betsy Varughese