AM6526: L2 Cache speed and configuration

The A53 cluster is at CPU clock including the L2 cache. There is no alternative configuration of clock speeds for L2 cache vs the rest of the cluster.

In the A53 TRM (TI uses standard A53, so all Arm documentation applies):

https://developer.arm.com/documentation/ddi0500/j/Functional-Description/Clocking-and-resets/Clocks?lang=en has

The Cortex-A53 processor has a single clock input, CLKIN. All cores in the Cortex-A53 processor and the SCU are clocked with a distributed version of CLKIN.

And SCU means the port from L2 cache https://developer.arm.com/documentation/ddi0500/j/Functional-Description/About-the-Cortex-A53-processor-functions/L2-memory-system?lang=en says:

SCU that connects the cores to the external memory system through the master memory interface. The SCU maintains data cache coherency between the cores and arbitrates L2 requests from the cores.

  Pekka