Hi Board Designers,
Refer additional inputs below
(+) TPS65219: TPS6521901 - Power management forum - Power management - TI E2E support forums
The AM243x MCU only supports VDD_CORE=0.85V and TPS6521901 has Buck1 configured to output 0.75V so it is not a good fit. Also, the ALX package does not support VDDS_DDR so you dont need a PMIC rail configured to output 1.1V or 1.2V.
For AM243x in ALX package we recommend using LP87334D. https://www.ti.com/lit/pdf/slda059
Here is a quick reference that might help to clarify but let us know if you have any questions.
Example connections
There is only a single Voltage Domain in the AM243x device which is shared between MCU and MAIN domains. This single voltage domain is then split between two PSC power domains (MCU_PSC and MAIN_PSC) which are then broken open into their multiple LPSC groupings. The separation of these two domains is to enable reset isolation, this does not translate to split voltage core voltage domains. Only MCU Domain IO and Analog supplies are isolated. The core supply is shared between MAIN and MCU domains.
To answer your question directly, the VDD_CORE supply is shared between R5F cores (MAIN domain) and M4F core (MCU domain)
1a. What is function of CAP_VDDSHV_MMC1?
[RR] The CAP_VDDSHV_MMC1 pin is routed to the output of the integrated SDIO_LDO0 3.3V to 1.8V LDO. If this LDO is used, this pin should be used to attach a 3.3uF capacitor to provide additional low-frequency stability to this LDO voltage regulator output.
SDIO_LDO0 is used to provide optional 3.3V or 1.8V signaling to the AM243x SDIO I/O pins depending on the status of V1P8_SIGNAL_ENA select.
V1P8_SIGNAL_ENA is set based on the MMCSD1 host controller SD_BUS_VOLTAGE selection set during the SD Bus Power Control sequence. See 12.3.5.5.1.3 SD Bus Power Control
Also, please see the diagram below to see this full MMC1 distribution path on the AM243x GP EVM.
The customer will use 3.3V fixed voltage for SD Card IO(switch function of 1.8V/3.3V will not be used).
1b. In this case, is it okay to apply 3.3V on VDDSHV5 directly?
[RR] If the SDIO_LDO0 is unused (and VDDA_3P3_SDIO is unused), then yes, you should be powering the VDDSHV5 directly from the same SDcard digital 3.3V source.
1c. When SDIO_LDO is not used, which VSS or 3.3uF should be connected on CAP_VDDSHV_MMC1?
Datasheet says "The CAP_VDDSHV_MMC1 pin must always be connected via a 3.3-μF ±20% capacitor to VSS" while it also says "If SDIO_LDO is not used to power VDDSHV5, each of these balls must be connected directly to VSS.".
[RR] In the case where the SDIO_LDIO is unused, the requirement to short VDDA_3P3_SDIO and CAP_VDDSHV_MMC1 to VSS should be followed. See AM243x datasheet, Table 6-85. Connectivity Requirements (ALV Package)
1d. EVM schematic looks like CAP_VDDSHV_MMC1 powers VDDSHV5(Not powered from external supply). However, datasheet doesn't explain details of CAP_VDDSHV_MMC1. Datasheet says "If SDIO_LDO is not used to power VDDSHV5, each of these balls must be connected directly to VSS.", but there is no explanation about "SDIO_LDO".
[RR] See my above reply to question 1a.
[#2]
2a. Is it okay to ramp up VDDA_3P3_SDIO after VDD_CORE?
[RR] Correct. It is OK to ramp VDDA_3P3_SDIO after VDD_CORE. This will be necessary in the case of the SDcard being powered down during the voltage SD_BUS_VOLTAGE selection sequence (see my above answer to 1a)
2b. You mentioned about VDDSHVx as below. Please make sure what about "VDDA_3P3_SDIO".
[RR] Right. Let me clarify that. This discussion was initially considering only the VDDA_3P3_SDIO and how that powered the VDDSHV5 (MMC1) pin group. What we found was that the VDDSHV5 and VDDA_3P3_SDIO power sequence requirements currently in the datasheet can be disregarded. The datasheet sequence for these power pins should be seen as a recommended startup sequence, but not a required startup sequence. There should be no problem cycling the VDDSHV5 and VDDA_3P3_SDIO power after VDD_CORE is enabled and even after PORz de-assertion and device startup.
We also found that the ability to sequence the VDDSHV5 before or after VDD_CORE could also be applied to all of the VDDSHVx I/O power groups.
We still recommend that you follow this datasheet sequence normally during initial startup, but if there is a need to cycle power any of these these VDDSHVx power domains after VDD_CORE and PORz, that will not casuse problems for the device.
Our customer would like to request for the pin attributes for AM64x in Excel format.
Here's a link to a similar file made for AM243x device:
/cfs-file/__key/communityserver-discussions-components-files/791/AM243x_5F00_ALV_5F00_ALX_5F00_PinAttributes.xlsx
The purpose of the request is that he wants to make sure if those 2 families (same package ALV) can be drop in replacement by comparison of their IO information.
Regards,
Sreenivasa
