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TDA4VH-Q1: power up sequence requirements

SH
Intellectual 420 points

Part Number: TDA4VH-Q1

Tool/software:

[I asked this question as a follow up topic for another topic, here (+) TDA4VH-Q1: power up sequence timing requirements - Processors forum - Processors - TI E2E support forums, but I got no feedback, so I am asking the same here]

For SoC power up, for its operation or reliability, does it matter if for example all 0.8V supply rails would NOT start to ramp up all at the same time, and would NOT finish ramping up at about the same time?

If instead, for example here the 0.8V supplies would be sequenced after one another, provided that the last 0.8V supply would still reach its operational voltage level before the next 0.85V and 1.1V supplies would start to ramp up?

(You could consider the same question applying to any or all of the supply rails, but I just use 0.8V supplies here as an example.)

  • 0
    TI__Expert 7655 points

    Sorry I did not get notified that you had a follow-up question,

    I've posted the reply below to the original E2E as well.

    Any individual input supply with the same voltage level and power up seq time step, can be enabled and ramp up at slightly different times and slew rates as long as all supplies within that time step group reach the Vopr min value before the next supply group begins to ramp.