AM623: Design guide information for 6 layer board

Hello Daniel, 

Thank you for the query.

There are differences in the number of high speed peripherals between AM62x and Am62L.

Any thoughts on the required peripherals including DDR memory type.

Regards,

Sreenivasa

Hi Sreenivasa

We plan to use 6 layers to design the PCB. I saw that AM62L uses 6 layers for EVB, and also attached the LAYER STACKUP file "TMDS62LEVM-6L-20-12-2023-[1639]". Can this be used as a reference for the layout of AM624?

Or do I have to follow the document "sprad06c_DDR bord design and layout guide"?

Thanks

Daniel

Hello Daniel,

Thank you.

Daniel Cheng1 said:

do I have to follow the document "sprad06c_DDR bord design and layout guide"?

The DDRSS IP is similar and the guidelines are also similar.

The pitch is 0.5mm for both and they use VCA.  

You could follow the AM62L if you are using similar peripherals. 

Regards,

Sreenivasa

Hello Daniel,

I suspect we have been discussing some of these in the below thread.

(+) AM623: Is there a reference layout file for six layers PCB design? - Processors forum - Processors - TI E2E support forums

Regards,

Sreenivasa

Hi Sreenivasa

Because the impedance of "AM62x DDR layout guide" is different from that of "TMD62LEVM-6L-20-12-2023-[1639]"; "AM62x DDR layout guide" is single 40 ohm, difference 80 ohm. TMD62LEVM-6L-20 is singlel 50 ohm, difference 100 ohm.

Thanks

Daniel

Hello Daniel, 

Are you considering a single 16-bit DDR memory in the design?

Regards,

Sreenivasa

Hello Daniel, 

The below FAQ could help:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1507805/faq-am62l-ddr4-guidelines-for-impedance-values?tisearch=e2e-sitesearch&keymatch=AM62L%20DDR4#

Regards,

Sreenivasa