DRA829J: Question About Errata i2183 - PCIe: Link up failure when unused lanes are not assigned to PCIe Controller

Hi Anthony,

I have not been able to find the internal E2E forum thread for this statement, so I do not have the context. However, that statement sounds like something I have said.

In any case, customer can reproduce the experiment by changing devicetree if they want to double confirm by seeing on a system at their end. Should be small changes where they change number of serdes lanes in the serdes node and number of lanes in PCIe node: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts?h=ti-linux-6.1.y#n857

Regards,

Takuma

Hi Takuma,

I'd like to add some details to this discussion. We can't really try out everything upfront as some of the connections have a binding, but yet provisional character in the design.

The used component is DRA829JMT5BALFRQ1. Due to the security vulnerability of SR1.1, we will upgrade to SR2.0 soon.

The envisioned configuration would be like that:

• SERDES0
  • PCIe0
    • Lane 0
  • CPSW0 SGMII
    • Lane 2
• SERDES1
  • PCIe1
    • Lane 0
  • CPSW0 SGMII
    • Lane 4
• SERDES2
  • USB1
    • USB 3.0
• SERDES3
  • PCIe3
    • Lane 0
    • Lane 1

The erratum is quite unspecific regarding the resulting functionality:

For example, link training fails if lanes 2 and 3 are assigned to another protocol while lanes 0 and 1 are used for PCIe to form a two lane link.

My questions are:

1. If one of the four SERDES blocks is configured as dual lane PCIe, I am not allowed to use anything except PCIe on the other SERDES blocks. Is that correct?
   Or the other way around: 
   I cannot implement a dual lane PCIe if I want to use anything else but PCIe in any other SERDES block.
2. Could you please check the above mentioned configuration and tell me whether it is valid / functional or not?

Kind regards

Wolfram

Hi Wolfram,

Thanks for the clarification, and understood what is desired. Let me check with the team on this.

To give some context:

• In our current 10.1 SDK, our default SERDES setting is PCIe for all SERDES0,1, and 2 lanes: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts?h=ti-linux-6.6.y#n509.
• In the past 8.6 SDK, we had SGMII as one of the lanes: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts?h=ti-linux-5.10.y#n511.
• Current SDK still has the old SERDES configuration, but it is a separate devicetree overlay which should still be functional: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/blame/arch/arm64/boot/dts/ti/k3-j721e-evm-ethfw.dtso?h=ti-linux-6.6.y

From this, I think your configuration is fine. However, my experience is mainly on the PCIe-side, so would like to check with team from SGMII perspective this is fine.

Regards,

Takuma

Hi Takuma,
Thanks for the feedback.
Yes please double check with the SGMII team and let us know.

-Related to the use case/configuration provided by Wolfram:
Is it possible on your side to create in sysconfig file of a configuration that we can confirm it is supported?
This is to ensure to have a known good reference for the SERDES config and associated pinmux.

https://dev.ti.com/sysconfig/#/config/?args=--device%20DRA829J%20--package%20%22FCBGA%20P$OPEN$ALFP$CLOSE$%22%20--variant%20defaul
Thanks in advance,

Anthony

Hi Anthony,

Checked with SGMII team, and it looks like:

"""

By default serdes0 we are using pcie + Qsgmii

In the latest SDK, linux side they are not configuring the Serdes for PCIe+ Qsgmii
It was configured at u-boot so linix will not re-configure.
If the customer is not using u-boot, they need to change the device tree in Linux while using TI EVM.

"""

So it looks like PCIe + SGMII is supported.

As for sysconfig, we don't have support for sysconfig configuring the SERDES. And the pins associated with SERDES do not have mux modes since they are dedicated to SERDES:

The Linux dts files and Linux SDK documentation can be used as reference for setting up SERDES.

Regards,

Takuma