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AM69A: SERDES4 USB not working

Juraj Golej
Prodigy 100 points
Part Number: AM69A
Other Parts Discussed in Thread: SK-AM69

Tool/software:

Hello,

in our custom board with AM69A MPU we want to use USB on SERDES4 lane 3. For simplicity, only the USB on the SERDES4 is enabled and all other SERDES blocks and protocols are disabled. Relevant part of the device tree:

&serdes_ln_ctrl {
	mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
					<0x8 0x3>, <0xc 0x3>, /* SERDES0 lane2/3 select */
					<0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */
					<0x18 0x3>, <0x1c 0x3>, /* SERDES1 lane2/3 select */
					<0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */
					<0x28 0x3>, <0x2c 0x3>, /* SERDES2 lane2/3 select */
					<0x40 0x3>, <0x44 0x3>, /* SERDES4 lane0/1 select */
					<0x48 0x3>, <0x4c 0x3>; /* SERDES4 lane2/3 select */

	idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_IP1_UNUSED>,
				  <J784S4_SERDES0_LANE2_PCIE3_LANE0>, <J784S4_SERDES0_LANE3_PCIE3_LANE1>,

				  <J784S4_SERDES1_LANE0_PCIE0_LANE0>, <J784S4_SERDES1_LANE1_QSGMII_LANE4>,
				  <J784S4_SERDES1_LANE2_PCIE2_LANE0>, <J784S4_SERDES1_LANE3_QSGMII_LANE2>,

				  <J784S4_SERDES2_LANE0_QSGMII_LANE5>, <J784S4_SERDES2_LANE1_QSGMII_LANE6>,
				  <J784S4_SERDES2_LANE2_QSGMII_LANE1>, <J784S4_SERDES2_LANE3_QSGMII_LANE8>,

				  <J784S4_SERDES4_LANE0_EDP_LANE0>, <J784S4_SERDES4_LANE1_EDP_LANE1>,
				  <J784S4_SERDES4_LANE2_QSGMII_LANE7>, <J784S4_SERDES4_LANE3_USB>;
};

&serdes_refclk {
	status = "okay";
	clock-frequency = <100000000>;
};

&serdes_wiz4 {
	status = "okay";
};

&serdes4 {
	status = "okay";

	serdes4_usb_link: phy@3 {
		reg = <3>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_USB3>;
		resets = <&serdes_wiz4 4>;
	};
};

&usb_serdes_mux {
	idle-states = <1>; /* USB0 to SERDES4 */
};

&usbss0 {
	status = "okay";
	pinctrl-0 = <&usb_main_pins_default>;
	pinctrl-names = "default";
	ti,vbus-divider;
};

&usb0 {
	status = "okay";
	dr_mode = "host";
	maximum-speed = "super-speed";
	phys = <&serdes4_usb_link>;
	phy-names = "cdns3,usb3-phy";
};

However, no USB is deceted in the lsusb. There is an error in dmesg:

[    5.998846] cdns-torrent-phy 5050000.serdes: Timeout waiting for CMN ready
[    5.998854] phy phy-5050000.serdes.10: phy poweron failed --> -110
[    5.998864] cdns-usb3: probe of 6000000.usb failed with error -110

Output from "k3conf dump clock 407":

|--------------------------------------------------------------------------------------------------------------------------------------|
| Device ID | Clock ID | Clock Name                                                            | Status              | Clock Frequency |
|--------------------------------------------------------------------------------------------------------------------------------------|
|   407     |     2    | DEV_SERDES_10G4_CLK                                                   | CLK_STATE_READY     | 125000000       |
|   407     |     3    | DEV_SERDES_10G4_CMN_REFCLK_M                                          | CLK_STATE_READY     | 0               |
|   407     |     3    | DEV_SERDES_10G4_CMN_REFCLK_M                                          | CLK_STATE_READY     | 0               |
|   407     |     4    | DEV_SERDES_10G4_CMN_REFCLK_P                                          | CLK_STATE_READY     | 0               |
|   407     |     4    | DEV_SERDES_10G4_CMN_REFCLK_P                                          | CLK_STATE_READY     | 0               |
|   407     |     5    | DEV_SERDES_10G4_CORE_REF1_CLK                                         | CLK_STATE_READY     | 156250000       |
|   407     |     6    | DEV_SERDES_10G4_CORE_REF_CLK                                          | CLK_STATE_READY     | 100000000       |
|   407     |     7    | DEV_SERDES_10G4_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT           | CLK_STATE_READY     | 25000000        |
|   407     |     8    | DEV_SERDES_10G4_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT            | CLK_STATE_READY     | 0               |
|   407     |     9    | DEV_SERDES_10G4_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | CLK_STATE_READY     | 156250000       |
|   407     |    10    | DEV_SERDES_10G4_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | CLK_STATE_READY     | 100000000       |
|   407     |    12    | DEV_SERDES_10G4_IP1_LN0_REFCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    13    | DEV_SERDES_10G4_IP1_LN0_RXCLK                                         | CLK_STATE_READY     | 0               |
|   407     |    14    | DEV_SERDES_10G4_IP1_LN0_RXFCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    15    | DEV_SERDES_10G4_IP1_LN0_TXCLK                                         | CLK_STATE_NOT_READY | 0               |
|   407     |    16    | DEV_SERDES_10G4_IP1_LN0_TXFCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    17    | DEV_SERDES_10G4_IP1_LN0_TXMCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    18    | DEV_SERDES_10G4_IP1_LN1_REFCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    19    | DEV_SERDES_10G4_IP1_LN1_RXCLK                                         | CLK_STATE_READY     | 0               |
|   407     |    20    | DEV_SERDES_10G4_IP1_LN1_RXFCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    21    | DEV_SERDES_10G4_IP1_LN1_TXCLK                                         | CLK_STATE_NOT_READY | 0               |
|   407     |    22    | DEV_SERDES_10G4_IP1_LN1_TXFCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    23    | DEV_SERDES_10G4_IP1_LN1_TXMCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    24    | DEV_SERDES_10G4_IP1_LN2_REFCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    25    | DEV_SERDES_10G4_IP1_LN2_RXCLK                                         | CLK_STATE_READY     | 0               |
|   407     |    26    | DEV_SERDES_10G4_IP1_LN2_RXFCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    27    | DEV_SERDES_10G4_IP1_LN2_TXCLK                                         | CLK_STATE_NOT_READY | 0               |
|   407     |    28    | DEV_SERDES_10G4_IP1_LN2_TXFCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    29    | DEV_SERDES_10G4_IP1_LN2_TXMCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    30    | DEV_SERDES_10G4_IP1_LN3_REFCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    31    | DEV_SERDES_10G4_IP1_LN3_RXCLK                                         | CLK_STATE_READY     | 0               |
|   407     |    32    | DEV_SERDES_10G4_IP1_LN3_RXFCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    33    | DEV_SERDES_10G4_IP1_LN3_TXCLK                                         | CLK_STATE_NOT_READY | 0               |
|   407     |    34    | DEV_SERDES_10G4_IP1_LN3_TXFCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    35    | DEV_SERDES_10G4_IP1_LN3_TXMCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    36    | DEV_SERDES_10G4_IP2_LN0_REFCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    37    | DEV_SERDES_10G4_IP2_LN0_RXCLK                                         | CLK_STATE_READY     | 0               |
|   407     |    38    | DEV_SERDES_10G4_IP2_LN0_RXFCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    39    | DEV_SERDES_10G4_IP2_LN0_TXCLK                                         | CLK_STATE_NOT_READY | 0               |
|   407     |    40    | DEV_SERDES_10G4_IP2_LN0_TXFCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    41    | DEV_SERDES_10G4_IP2_LN0_TXMCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    42    | DEV_SERDES_10G4_IP2_LN1_REFCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    43    | DEV_SERDES_10G4_IP2_LN1_RXCLK                                         | CLK_STATE_READY     | 0               |
|   407     |    44    | DEV_SERDES_10G4_IP2_LN1_RXFCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    45    | DEV_SERDES_10G4_IP2_LN1_TXCLK                                         | CLK_STATE_NOT_READY | 0               |
|   407     |    46    | DEV_SERDES_10G4_IP2_LN1_TXFCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    47    | DEV_SERDES_10G4_IP2_LN1_TXMCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    48    | DEV_SERDES_10G4_IP2_LN2_REFCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    49    | DEV_SERDES_10G4_IP2_LN2_RXCLK                                         | CLK_STATE_READY     | 0               |
|   407     |    50    | DEV_SERDES_10G4_IP2_LN2_RXFCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    51    | DEV_SERDES_10G4_IP2_LN2_TXCLK                                         | CLK_STATE_NOT_READY | 0               |
|   407     |    52    | DEV_SERDES_10G4_IP2_LN2_TXFCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    53    | DEV_SERDES_10G4_IP2_LN2_TXMCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    54    | DEV_SERDES_10G4_IP2_LN3_REFCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    55    | DEV_SERDES_10G4_IP2_LN3_RXCLK                                         | CLK_STATE_READY     | 0               |
|   407     |    56    | DEV_SERDES_10G4_IP2_LN3_RXFCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    57    | DEV_SERDES_10G4_IP2_LN3_TXCLK                                         | CLK_STATE_NOT_READY | 0               |
|   407     |    58    | DEV_SERDES_10G4_IP2_LN3_TXFCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    59    | DEV_SERDES_10G4_IP2_LN3_TXMCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    78    | DEV_SERDES_10G4_IP3_LN3_REFCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    79    | DEV_SERDES_10G4_IP3_LN3_RXCLK                                         | CLK_STATE_READY     | 0               |
|   407     |    80    | DEV_SERDES_10G4_IP3_LN3_RXFCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    81    | DEV_SERDES_10G4_IP3_LN3_TXCLK                                         | CLK_STATE_READY     | 0               |
|   407     |    82    | DEV_SERDES_10G4_IP3_LN3_TXFCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    83    | DEV_SERDES_10G4_IP3_LN3_TXMCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    84    | DEV_SERDES_10G4_IP4_LN0_REFCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    85    | DEV_SERDES_10G4_IP4_LN0_RXCLK                                         | CLK_STATE_READY     | 0               |
|   407     |    86    | DEV_SERDES_10G4_IP4_LN0_RXFCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    87    | DEV_SERDES_10G4_IP4_LN0_TXCLK                                         | CLK_STATE_NOT_READY | 0               |
|   407     |    88    | DEV_SERDES_10G4_IP4_LN0_TXFCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    89    | DEV_SERDES_10G4_IP4_LN0_TXMCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    90    | DEV_SERDES_10G4_IP4_LN1_REFCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    91    | DEV_SERDES_10G4_IP4_LN1_RXCLK                                         | CLK_STATE_READY     | 0               |
|   407     |    92    | DEV_SERDES_10G4_IP4_LN1_RXFCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    93    | DEV_SERDES_10G4_IP4_LN1_TXCLK                                         | CLK_STATE_NOT_READY | 0               |
|   407     |    94    | DEV_SERDES_10G4_IP4_LN1_TXFCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    95    | DEV_SERDES_10G4_IP4_LN1_TXMCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    96    | DEV_SERDES_10G4_IP4_LN2_REFCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    97    | DEV_SERDES_10G4_IP4_LN2_RXCLK                                         | CLK_STATE_READY     | 0               |
|   407     |    98    | DEV_SERDES_10G4_IP4_LN2_RXFCLK                                        | CLK_STATE_READY     | 0               |
|   407     |    99    | DEV_SERDES_10G4_IP4_LN2_TXCLK                                         | CLK_STATE_NOT_READY | 0               |
|   407     |   100    | DEV_SERDES_10G4_IP4_LN2_TXFCLK                                        | CLK_STATE_READY     | 0               |
|   407     |   101    | DEV_SERDES_10G4_IP4_LN2_TXMCLK                                        | CLK_STATE_READY     | 0               |
|   407     |   102    | DEV_SERDES_10G4_IP4_LN3_REFCLK                                        | CLK_STATE_READY     | 0               |
|   407     |   103    | DEV_SERDES_10G4_IP4_LN3_RXCLK                                         | CLK_STATE_READY     | 0               |
|   407     |   104    | DEV_SERDES_10G4_IP4_LN3_RXFCLK                                        | CLK_STATE_READY     | 0               |
|   407     |   105    | DEV_SERDES_10G4_IP4_LN3_TXCLK                                         | CLK_STATE_NOT_READY | 0               |
|   407     |   106    | DEV_SERDES_10G4_IP4_LN3_TXFCLK                                        | CLK_STATE_READY     | 0               |
|   407     |   107    | DEV_SERDES_10G4_IP4_LN3_TXMCLK                                        | CLK_STATE_READY     | 0               |
|--------------------------------------------------------------------------------------------------------------------------------------|

What can be the possible cause of this error?

On the SERDES4 we have also a DisplayPort and SGMII output. SGMII has the same problem as USB. DisplayPort works fine.

  • 0
    TI__Genius 12910 points

    Hi Juraj,

    Sorry for the late reply.

    You can only use 2 protocols at a time.Hence EDP+USB or SGMII+USB.

    Regards

    Gokul

  • 0 in reply to Gokul Praveen
    Prodigy 100 points

    Hi Gokul,

    I changed the idle-states property to match the &serdes4 DT node. However, the same error still occurs.

    idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_IP1_UNUSED>,
			<J784S4_SERDES0_LANE2_PCIE3_LANE0>, <J784S4_SERDES0_LANE3_PCIE3_LANE1>,

			<J784S4_SERDES1_LANE0_PCIE0_LANE0>, <J784S4_SERDES1_LANE1_QSGMII_LANE4>,
			<J784S4_SERDES1_LANE2_PCIE2_LANE0>, <J784S4_SERDES1_LANE3_QSGMII_LANE2>,

			<J784S4_SERDES2_LANE0_QSGMII_LANE5>, <J784S4_SERDES2_LANE1_QSGMII_LANE6>,
			<J784S4_SERDES2_LANE2_QSGMII_LANE1>, <J784S4_SERDES2_LANE3_QSGMII_LANE8>,

			<J784S4_SERDES4_LANE0_IP3_UNUSED>, <J784S4_SERDES4_LANE1_IP3_UNUSED>,
			<J784S4_SERDES4_LANE2_IP3_UNUSED>, <J784S4_SERDES4_LANE3_USB>;

  • 0 in reply to Juraj Golej
    TI__Genius 12910 points

    Hi Juraj,

    Can you provide the hardware schematics of USB and serdes of the custom board,so that we can analyze it.

    Regards

    Gokul

  • 0 in reply to Gokul Praveen
    Prodigy 100 points

    Hi, Gokul,

    here are parts of the USB and SERDES4 schematics. If you need more parts, write.

    We have connected 3 types of peripherals to SERDES4, but only 2 of them will be used. The USB hub is copied from the SK-AM69 development kit.

    serdes_cropped.pdf

    usb-hub_cropped.pdf

  • 0 in reply to Juraj Golej
    TI__Genius 12910 points

    Hi Juraj,

    Sorry for the delayed response.

    I have requested the respective hardware expert to review the schematics.Thanks in advance for your patience.

    Regards

    Gokul

  • 0 in reply to Gokul Praveen
    TI__Guru 53155 points

    Have you verified USB_DRVVBUS being asserted? 

    I'm not sure you can use USB + SGMII on lanes 2 and 3.  I think if USB is selected, it enables USB on both Lanes 2 and Lanes 3 (USB Type C support), even though only 1 is enabled at a time.  (Others copied on this E2E thread can confirm - more familiar with programming the interface.)

  • 0 in reply to Robert Eschler
    TI__Genius 12910 points

    Hi Robert

    Robert Eschler said:
    I'm not sure you can use USB + SGMII on lanes 2 and 3.  I think if USB is selected, it enables USB on both Lanes 2 and Lanes 3 (USB Type C support), even though only 1 is enabled at a time.  (Others copied on this E2E thread can confirm - more familiar with programming the interface.)

    I had requested them that change and they are facing errors even after that.They are now only using LANE3 for USB and all other lanes are unused in SERDES4.

    In addition to that as per the error logs which they are getting phy poweron is failing.So I am suspecting if they have set the hardware properly.

    [    5.998846] cdns-torrent-phy 5050000.serdes: Timeout waiting for CMN ready
[    5.998854] phy phy-5050000.serdes.10: phy poweron failed --> -110
[    5.998864] cdns-usb3: probe of 6000000.usb failed with error -110

    Regards

    Gokul

  • +1 in reply to Gokul Praveen
    Prodigy 100 points

    Hello,

    I found the problem. The "reg" property of the "serdes_ln_ctrl" DT node has an invalid length, so I changed it from 0x30 to 0x50 and now the USB works in SuperSpeed mode.It simply does not set the mux for SERDES4 lines, because only the first 3 SERDES are defined in k3-j784s4-main.dtsi. I don't know why.

    reg = <0x00004080 0x50>;

    The complete "serdes_ln_ctrl" node is now (only USB is enabled for now):

    &serdes_ln_ctrl {
	reg = <0x00004080 0x50>;
	mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
					<0x8 0x3>, <0xc 0x3>, /* SERDES0 lane2/3 select */
					<0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */
					<0x18 0x3>, <0x1c 0x3>, /* SERDES1 lane2/3 select */
					<0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */
					<0x28 0x3>, <0x2c 0x3>, /* SERDES2 lane2/3 select */
					<0x40 0x3>, <0x44 0x3>, /* SERDES4 lane0/1 select */
					<0x48 0x3>, <0x4c 0x3>; /* SERDES4 lane2/3 select */

	idle-states = <J784S4_SERDES0_LANE0_IP1_UNUSED>, <J784S4_SERDES0_LANE1_IP1_UNUSED>,
				  <J784S4_SERDES0_LANE2_IP4_UNUSED>, <J784S4_SERDES0_LANE3_IP4_UNUSED>,

				  <J784S4_SERDES1_LANE0_IP3_UNUSED>, <J784S4_SERDES1_LANE1_IP3_UNUSED>,
				  <J784S4_SERDES1_LANE2_IP4_UNUSED>, <J784S4_SERDES1_LANE3_IP4_UNUSED>,

				  <J784S4_SERDES2_LANE0_IP2_UNUSED>, <J784S4_SERDES2_LANE1_IP2_UNUSED>,
				  <J784S4_SERDES2_LANE2_IP3_UNUSED>, <J784S4_SERDES2_LANE3_IP3_UNUSED>,

				  <J784S4_SERDES4_LANE0_IP3_UNUSED>, <J784S4_SERDES4_LANE1_IP3_UNUSED>,
				  <J784S4_SERDES4_LANE2_IP3_UNUSED>, <J784S4_SERDES4_LANE3_USB>;
};

    Thank you very much for your support.