DRA829J: Procedure to change clock source

Hi,

Usually, after stopping the peripheral, you need to change/set the clock.
We have a Sciclient API call for the module ON/OFF.

Plese refer to below API Guide of Scliclient for more detials.
https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/10_01_00_04/exports/docs/pdk_jacinto_10_01_00_25/docs/apiguide/j721e/html/group__SCICLIENT__FMW__PM__IF.html#ga329b967edc51edad7a5ac1a1b86a2035

Antonio Pinto said:

Can you clarify please, whether we can change parent clock without triggering RST signal to a peripheral afterwards?

Parent clock not allowed to change for a few modules, which use the same PLL used by other modules.

Best Regards,
Sudheer

Hi Sudheer,
Thanks for your quick response.

Actually we are not using the API referred in your answer.
We are performing board configuration on MCU_R5F core only, with no interaction with M3 core (SYSFW).
This is our sequence:
    1. PLL configuration
    2. Clock selection (it only sets the CLK_SEL bitfield)
    3. Power configuration

Therefore we have a dedicated interface to select the source clock for each module.
Using this approach, do we need to trigger a RST signal after changing the parent clock in #2?

Doredla Sudheer Kumar said:

Parent clock not allowed to change for a few modules, which use the same PLL used by other modules.

Where can we find the list of modules which Parent Clock is not allowed to be changed?
Are there any modules, that even though they have multiple clock selection options, can't be changed (hardware wise)?

Thank you.
António

Hi,

Antonio Pinto said:

This is our sequence:
    1. PLL configuration
    2. Clock selection (it only sets the CLK_SEL bitfield)
    3. Power configuration

Are you using "Board_init" with receptive configuration like "BOARD_INIT_PLL", "BOARD_INIT_MODULE_CLOCK"
The above will use sciclient calls at the end for RM, PM configuration.

Antonio Pinto said:

Therefore we have a dedicated interface to select the source clock for each module.
Using this approach, do we need to trigger a RST signal after changing the parent clock in #2?

If you are directly changing the clock source of the module, you are supposed to perform a module OFF before the clock change and an ON after.
Please refer to the TI examples from the SDKs for more details.

Antonio Pinto said:

Are there any modules, that even though they have multiple clock selection options, can't be changed (hardware wise)?

You can change the clock for all modules that have multiple clock sources.

Antonio Pinto said:

Doredla Sudheer Kumar said:

Parent clock not allowed to change for a few modules, which use the same PLL used by other modules.

Where can we find the list of modules which Parent Clock is not allowed to be changed?

What I mean above is that changing of PLL frequency is not allowed, as multiple HSDIVs depend on the PLL frequency.
When you tried to change the clock frequency, not able to success means that changing of clock is not supported for that.

Best Regards,
Sudheer