Tool/software:
Hi,
For HW validation, we would like to disable cache to make sure all data are raw and direct data. However, if I comment out the cache_enable under this function, whole application will not boot up. Is there a way to be in a cache-free environment?
Hi Dazong,
You can configure this from sysconfig for a particular memory region. In the MMU ARMv8 Configurations, you have to set the Attribute property of a particular Memory region to Attr Index 4: Normal inner & outer non-cacheable, if you want to make it non-cacheable. Please refer to the example below where I am setting the attribute of DDR_REGION to make it non-cacheable:
Best Regards,
Meet.
Hi Meet,
On my side I tried two thing
1. follow exactly your screen shot including the region address and region size
2. not changing the region address setting but only changes attribute to index 4
Both are not working.
I tried to debug example code but got error msg <Source file 'portable\GCC\ARM_CA53\portASM.S' was not found.>
Then I tried debug my own project, I see both cases it will enters infinite while loop at
MmuP_RegionConfig gMmuRegionConfig[CONFIG_MMU_NUM_REGIONS] =
{
{
.vaddr = 0x0u,
.paddr = 0x0u,
.size = 0x80000000u,
.attr = {
.accessPerm = MMUP_ACCESS_PERM_PRIV_RW_USER_NONE,
.privExecute = 1,
.userExecute = 0,
.shareable = MMUP_SHARABLE_OUTER,
.attrIndx = MMUP_ATTRINDX_MAIR0,
.global = 1
}
},
{
.vaddr = 0x82000000u,
.paddr = 0x82000000u,
.size = 0x02000000u,
.attr = {
.accessPerm = MMUP_ACCESS_PERM_PRIV_RW_USER_NONE,
.privExecute = 1,
.userExecute = 0,
.shareable = MMUP_SHARABLE_OUTER,
.attrIndx = MMUP_ATTRINDX_MAIR4,
.global = 1
}
},
};MmuP_RegionConfig gMmuRegionConfig[CONFIG_MMU_NUM_REGIONS] =
{
{
.vaddr = 0x0u,
.paddr = 0x0u,
.size = 0x80000000u,
.attr = {
.accessPerm = MMUP_ACCESS_PERM_PRIV_RW_USER_NONE,
.privExecute = 1,
.userExecute = 0,
.shareable = MMUP_SHARABLE_OUTER,
.attrIndx = MMUP_ATTRINDX_MAIR0,
.global = 1
}
},
{
.vaddr = 0x80000000u,
.paddr = 0x80000000u,
.size = 0x80000000u,
.attr = {
.accessPerm = MMUP_ACCESS_PERM_PRIV_RW_USER_NONE,
.privExecute = 1,
.userExecute = 0,
.shareable = MMUP_SHARABLE_OUTER,
.attrIndx = MMUP_ATTRINDX_MAIR4,
.global = 1
}
},
};Thanks,
Dazong
Hello Dazong,
Please try the following MPU configuration settings:
• Place the ATF code in cached DDR memory.
• Keep the Application in uncached DDR memory.
• Ensure the AMP shared buffer resides in cached memory.
I have attached my code for your reference.
Please note:
If you move any part of the DDR memory to uncached, performance will degrade.
If this degradation is acceptable for your use case, you may proceed with these settings.
Otherwise, it’s recommended to keep everything in cached memory for better performance.
Code :
Please let me know if you face any issues ..
Regards,
Anil.
Hey Anil,
It seems this update is causing some errors with our I2C testing when running at 100 kHz but works fine at 400kHz. Do you have any idea why this could be. Program is getting hung up here
Hello Brody ,
Can you please open new thread for new queries (try to post in a private forum)?
Did you put the break point in the Master ISR and see from where the exception is going ?
Did you change any FCLK frequency of the I2C when you operated at 100KZ? What is the I2C FCLK ?
Are you trying the above testing in cache enabled or disabled ?
Regards,
Anil.
Hey Anil,
I think I will keep the discussion here since it is related to the cache disable. So, what I did to test is I took the same setup and code you provided for mmc example and I was able to build and run the exampel mmc code. However, when I copy the setup for MMU ARMv8 to the I2C led blink example, as soon I change Attribute on the DDR_MEM_REGION from Attr Index 7 to Attr Index 4, this example code for I2C Led blink will not work
Could you please try on your side to mimic the same setup described above for the MMC example for MMU ARMv8 and see if you are able to use it to run the I2C led blink example.
Thanks
i2c_led_blink_am62lx-evm_a53ss0-0_nortos_gcc-aarch64.zip