AM625: Custom board bring up with MCU SDK

Snagboot is based on DFU for UBOOT, spl need to build with dfu enabled. How to do it with SBL?

Hi Tony,

Tony Tang said:

How to do it with SBL?

When you say how to do it with SBL, please elaborate what all images need to be flashed from the customer's end then I can comment further.

Regards,

Vaibhav

Customer will use RTOS SDK with AM6254, application runs on A53, Autosar runs on R5F.

Hi Tony,

Tony Tang said:

RTOS SDK with AM6254

By RTOS SDK, I am assuming you meant MCU PLUS SDK AM62x.

The MCU PLUS SDK AM62x, does not have native support for USB Stack. If you want to leverage flashing via usb, customer needs to generate u-boot images, then they can flash any image via DFU.

Else the other option(which exists) is UART Uniflash. 

Regards,

Vaibhav

Hi Vaibhav,

In order to flashing custom board, what file need to be modified/replaced and rebuild? I think the stage2 file also need to rebuild, did not see where mentioned it. 

Hi Tony,

I believe in order to identify what all files need to be modified, we can follow the following steps:

1. Suppose I would like my configuration to follow whats mentioned here:
   
2. Then we need to rebuild every file mentioned here, to make sure the changes to  board_ddrReginit.h and any external flash configurations are taken care of. [You can ignore the line number 23 in the above file for the time being]
3. As a safe measure it would be okay to rebuild all the libraries: mainly the ones under source/board and source/drivers.

Regards,

Vaibhav

That is why I am asking for a custom board bring up guide, which will save a lot of time for who are not familiar with TI software.

rebuild all can't help customer understand the boot procedure, flashing procedure, etc.

Now customer can't flash although rebuild with own sysconfig ddr.h file.

I suspect it is DDR problem, but how to debug it with MCU SDK?

Tony Tang said:

That is why I am asking for a custom board bring up guide

Hi Tony,

This is in progress.

For DDR related issues, I have assigned this to another expert.

Regards,

Vaibhav

I meant how to debug DDR with MCU SDK, as can't connect A53 to init from gel file.

Hi Vaibhav,

As James is out of duty until June 1x. Do you have suggestion on how to debug DDR when bring up with MCU SDK? This is my first customer use MCU SDK with AM62x. 

Can I connect to R5F after download stage 1 and stage 2 to observe and reinit DDR in CCS, and it won't reset and lose JTAG connection?

Tony Tang said:

I suspect it is DDR problem, but how to debug it with MCU SDK?

This cannot be a DDR problem as the SBL Uniflash Stage1 receives the Stage2 in DDR and boots it from there. As the STATUS of Stage2 is SUCCESS that means the Stage1 was able to boot the Stage2 successfully.

I think the issue is in the Stage2 itself because of the custom flash part.

I see from the logs that the customer is using "am62x-sk-lp" images. Please note the default Uniflash Stage2 example for this board would have NAND flash and eMMC enabled in the Sysconfig.

So, does the customer has NAND and eMMC flash parts available on their board?

Good to know the DDR is working. the PHY mode impacted. Now NULL SBL can boot to below part,

It should be " Bootloader_loadSelfCpu ” of below SK board output log. This should not be difference between EVM and custom board.

  INFO: Bootloader_runCpu:176: CPU m4f0-0 is initialized to 400000000 Hz !!!
  INFO: Bootloader_runCpu:176: CPU a530-0 is initialized to 1400000000 Hz !!!
  INFO: Bootloader_runCpu:176: CPU a530-1 is initialized to 1400000000 Hz !!!
  INFO: Bootloader_runCpu:176: CPU a531-0 is initialized to 1400000000 Hz !!!
  INFO: Bootloader_runCpu:176: CPU a531-1 is initialized to 1400000000 Hz !!!
  INFO: Bootloader_loadSelfCpu:229: CPU r5f0-0 is initialized to 400000000 Hz !!!
  INFO: Bootloader_JumpSelfCpu:248: All done, jumping self ...

Please suggest...

PS. The LP-DDR4 size on custom board is 512MB.

Try disabling the DMA enabled in one of the bootloader instance of the SBL's Sysonfig. It should help if the issue is because of the DMA alone.

It works by disabling DDR Inline ECC in SBL, can it be explained? 

Tony Tang said:

It works by disabling DDR Inline ECC in SBL, can it be explained? 

If DDR Inline ECC is enabled, last 1/9th address space is reserved. Given 512MB DDR, the last ~56MB would be reserved and hence the failure. If the ECC is kept enabled, the WKUP R5F application address space has to be accordingly adjusted.

But sysconfig dd not detect the over boundary, should it?

Assigned to safety expert for the clarification!!

Hello Tony,

The linker command file is not generated as a part of syscfg tool in AM62 devices. Also, since we enable inline ECC in SBL and define the DDR regions in Wkup R5 application linker, there is no way for syscfg to throw an error. We have to manually ensure that any of the cores do not access the last 1/9th region of the DDR.

Tony Tang said:

But sysconfig dd not detect the over boundary, should it?

The last point in the screenshot talks about the scenario where the ECC region exceeding the 8/9th of the DDR space and goes into 1/9th reserved region. 

Regards,

Nihar Potturu. 

Hello Nihar,

Thank you. 

Last questions:

#1. What is ECC region, there is only 4 ECC region in sysconfig, while the index calculated by size. what is the index used for?

#2. What is the last 1/9 space used for ECC, store ECC result?